Intel vs TSMC in Risk Taking

[Daniel Nenni]

I plucked this quote from an IEEE article:

“Intel used to be the conservative one,” says Dan Hutcheson, vice chair of TechInsights. Previously, TSMC was more aggressive in its risk-taking, and the company more frequently missed the mark. Now, the situation has flipped, Hutcheson explains. “It’s a very risky move to try to implement two major technology changes at once, and in the past this has often been a recipe for disaster,” he says.

He is talking about Intel 20A with backside power delivery (BPD). I never considered TSMC a risk taker. They have customers to serve and their corporate lives depend on it (Trusted Foundry) . Examples: TSMC split double patterning at 20nm with FinFETs at 16nm. TSMC added EUV layers to 7nm (7nm+) after it was in HVM. That is not aggressive risk-taking, my opinion.

Intel on the other hand serves itself with internal developed products that can and have been delayed due to process issues. Intel risked doing double patterning and FinFETs at 14nm and did quite well. It was done in a stealthy manner so we do not know about delays and such but it was a very disruptive move. Intel risked doing 10/7nm without EUV and failed badly. For Intel the difference is that now they have competitive pressure at the product (AMD) and process (TSMC) level which they did not have before.

I also disagree with the quote about 20A with BPD being a risky move. Intel is bringing 20A to HVM then adding backside power delivery. Same with 18A, you are not required to do backside power delivery. Intel 18A stands on its own as an innovative process that is competitive with TSMC N2 and Samsung 2nm, even beating them to market. With backside power delivery Intel leap frogs ahead until TSMC and Samsung delivers BPD it a year or two later.

Correct me if I am wrong here but that quote in the context it was presented is nonsense.

In 2024, Intel Hopes to Leapfrog Its Chipmaking Competitors

The chipmaker is betting on new transistors and power-delivery tech

spectrum.ieee.org

 

[hist78]

I plucked this quote from an IEEE article:

“Intel used to be the conservative one,” says Dan Hutcheson, vice chair of TechInsights. Previously, TSMC was more aggressive in its risk-taking, and the company more frequently missed the mark. Now, the situation has flipped, Hutcheson explains. “It’s a very risky move to try to implement two major technology changes at once, and in the past this has often been a recipe for disaster,” he says.

He is talking about Intel 20A with backside power delivery (BPD). I never considered TSMC a risk taker. They have customers to serve and their corporate lives depend on it (Trusted Foundry) . Examples: TSMC split double patterning at 20nm with FinFETs at 16nm. TSMC added EUV layers to 7nm (7nm+) after it was in HVM. That is not aggressive risk-taking, my opinion.

Intel on the other hand serves itself with internal developed products that can and have been delayed due to process issues. Intel risked doing double patterning and FinFETs at 14nm and did quite well. It was done in a stealthy manner so we do not know about delays and such but it was a very disruptive move. Intel risked doing 10/7nm without EUV and failed badly. For Intel the difference is that now they have competitive pressure at the product (AMD) and process (TSMC) level which they did not have before.

I also disagree with the quote about 20A with BPD being a risky move. Intel is bringing 20A to HVM then adding backside power delivery. Same with 18A, you are not required to do backside power delivery. Intel 18A stands on its own as an innovative process that is competitive with TSMC N2 and Samsung 2nm, even beating them to market. With backside power delivery Intel leap frogs ahead until TSMC and Samsung delivers BPD it a year or two later.

Correct me if I am wrong here but that quote in the context it was presented is nonsense.

In 2024, Intel Hopes to Leapfrog Its Chipmaking Competitors

The chipmaker is betting on new transistors and power-delivery tech

spectrum.ieee.org

"“Intel used to be the conservative one,” says Dan Hutcheson, vice chair of TechInsights. Previously, TSMC was more aggressive in its risk-taking, and the company more frequently missed the mark. "

I thought Intel, not TSMC, used to be aggressive and kept missing its target delivery dates.

 

[nghanayem]

I assume his TSMC comment was in relation to DUV immersion, Cu, and non SiO2 ILDs. In these specific cases intel took the more “conservative” approach. What he failed to mention was that intel was taking all of their risk on the transistor side. I can’t remember if it was 65 or 45nm that used double patterning for gates with KrF, but I think it was 45nm, since I think it was either TI or one of the Japanese semi firms that did the same thing (at least if I am remembering David Kanter’s IEDM 08 coverage correctly). Assuming it was 45, yeah intel was conservative on litho but they were like what 5 years ahead of TSMC 28nm HVM.

As for intel’s risk management on 20A, I don’t really understand this concern. Intel talked about how they are derisking 20A’s BEOL with an intel 4/3 FEOL years ago. Heck at VLSI intel was touting how an 8 e-core cpu had a defect trend that was only trailing intel 4 by something like 2Qs. A quarter later we learned at intel innovation that mtl compute die yields are better than skylake or tigerlake were at launch even after normalizing for die size. As for your statement that BSPDN comes later where did you hear that Dan? Intel has never once talked about a FSPD option. Correct me if I am wrong but during earnings intel always said something to the tune of “Our Arrowlake processor featuring the two breakthrough innovations of ribbbonfet AND powervia". In my opinion if powervia is already derisked and they figured out the assembly test part as well as intel claims they have at VLSI, I don’t see why you would waste even a microsecond of time on a FSPDN 20A. Especially if it would cost more like intel claims intel 4 with FSPDN does.

The EUV thing always ticks me off. Let’s say intel committed to EUV from day one. Okay so considering TSMC didn’t even do a full insertion of EUV in 2019 and waited until N5 in 2020, and that Samsung couldn’t get 7LPP to not be vaporware until like 2019/2020. Why would anyone expect that Cannon lake would have come out in 2017 (or even 2018 for that matter) if intel used EUV for 10nm? In my opinion if anything 10nm would have been just as if not more late. The mistake goes to my first paragraph; finding the appropriate amount of risk. It makes me wonder what a 10nm with low 40s nm min metal pitch so you could do SADP metals would look. It would then be interesting to see how it would have turned out.

 

[Xebec]

Intel also reduced risk on BPD by doing a limited volume internal test node with it before 20A:

To test its PowerVia backside power delivery network, Intel built a special manufacturing process based on its Intel 4 node that uses proven FinFET transistors, but it comes with a backside power rail instead of a traditional power rail. This process is naturally called Intel 4 + PowerVia and it is used for one test chip codenamed Blue Sky Creek.

(Source: https://www.tomshardware.com/news/i...lled,based on the Crestmont microarchitecture.)

 

[hskuo]

I plucked this quote from an IEEE article:

“Intel used to be the conservative one,” says Dan Hutcheson, vice chair of TechInsights. Previously, TSMC was more aggressive in its risk-taking, and the company more frequently missed the mark. Now, the situation has flipped, Hutcheson explains. “It’s a very risky move to try to implement two major technology changes at once, and in the past this has often been a recipe for disaster,” he says.

He is talking about Intel 20A with backside power delivery (BPD). I never considered TSMC a risk taker. They have customers to serve and their corporate lives depend on it (Trusted Foundry) . Examples: TSMC split double patterning at 20nm with FinFETs at 16nm. TSMC added EUV layers to 7nm (7nm+) after it was in HVM. That is not aggressive risk-taking, my opinion.

Intel on the other hand serves itself with internal developed products that can and have been delayed due to process issues. Intel risked doing double patterning and FinFETs at 14nm and did quite well. It was done in a stealthy manner so we do not know about delays and such but it was a very disruptive move. Intel risked doing 10/7nm without EUV and failed badly. For Intel the difference is that now they have competitive pressure at the product (AMD) and process (TSMC) level which they did not have before.

I also disagree with the quote about 20A with BPD being a risky move. Intel is bringing 20A to HVM then adding backside power delivery. Same with 18A, you are not required to do backside power delivery. Intel 18A stands on its own as an innovative process that is competitive with TSMC N2 and Samsung 2nm, even beating them to market. With backside power delivery Intel leap frogs ahead until TSMC and Samsung delivers BPD it a year or two later.

Correct me if I am wrong here but that quote in the context it was presented is nonsense.

In 2024, Intel Hopes to Leapfrog Its Chipmaking Competitors

The chipmaker is betting on new transistors and power-delivery tech

spectrum.ieee.org

I would say TSM was more conservative in the past 30 years until there is no new process innovation to be learned from process technology leading companies like intel or IBM in around 2018. From then, tsmc delivered new process technologies almost on time and more robust with the order/Volume support from Apple or Hisilicon in 5nm ramp-up. Intel is the first company to introduce strain engineering, gate last HKMG, FinFET and COAG, but screwed up from 10nm node. Samsung was the first company to put EUV, Nansheet MOS in HVM but do not get the advantage of early adoption. It used to be SEMATECH as the leading technology pathfinding consortium. SEMATECH project was closed and now imec takes the role. imec has talked and worked on GAA/Nanosheet/Forksheet/CFET in transistor architecture migration and front-side BPR, backside PDN for years. It is not new but who will be the first company adopted it in HVM and implement this DTCO to get better PPA with volume is the key. Now we have STCO or 3DIC (chiplet) integration on the road also. The inter-operability between technologies/vendors might take a while and the paradigm shift is expected. 5 nodes in 4 years are not easy tasks and mean more risk taking now. It would be doubtable, especially the old team screwed up before and the new team still needs to prove it successfully with more risks and shorter time. The competition is on the way. Go for three major contestants.

 

[semiman]

It's really hard to summarize complex technological decisions into single word. Intel decided to wait for EUV methologies and throughput to increase, while using drastic new measures(COAG, Cobalt metals...etc), to increase densities using DUV. So Intel was risk taker of transistor manufacturing, but somwehat conservative of equipment(only in litho, since they used cobalt equip)

Now it's reversed. Intel decided to use High NA first, then adopt schemes one by one. Intel started production of Foveros in 2018, but now in mass production, showing that they're waiting for a maturity.

 

[Tanj]

To test its PowerVia backside power delivery network, Intel built a special manufacturing process based on its Intel 4 node that uses proven FinFET transistors, but it comes with a backside power rail instead of a traditional power rail. This process is naturally called Intel 4 + PowerVia and it is used for one test chip codenamed Blue Sky Creek.

Also 4+ was in the public reveal at 2023 symposium in Japan, https://community.intel.com/t5/Blog...ology-Among-Seven-Papers-at-VLSI/post/1494944

It is awesome when you see a cross-section and realize there is just a micron-thick smear remaining from the original Si crystal wafer. Both front and back are metals and insulators.

 

[Fred Chen]

Samsung is considered first to EUV, but the benefits it reaped from being so can obviously be debated.

 

[Fred Chen]

Backside power is considered by Intel its next paradigm shift (like strained silicon and high-k metal gate). https://www.tomshardware.com/news/intel-details-powervia-backside-power-delivery-network

There are still some risks with this approach. NanoTSVs are used instead of buried power rails, for example. While not yet pointed out as a significant risk, cooling will require some new approaches.

 

[Tanj]

There are still some risks with this approach. NanoTSVs are used instead of buried power rails, for example. While not yet pointed out as a significant risk, cooling will require some new approaches.

I'm curious how perf holds up on a device where there is no longer a silicon substrate, just a thin film of active silicon sandwiched between metal and insulator structures which are far thicker. The strain on the silicon will vary with temperature.

I do think the BSPDN will be compatible with heat removal, but these devices may need direct liquid cooling over constrained temperature range to perform properly.

 

[semiman]

I'm curious how perf holds up on a device where there is no longer a silicon substrate, just a thin film of active silicon sandwiched between metal and insulator structures which are far thicker. The strain on the silicon will vary with temperature.

I do think the BSPDN will be compatible with heat removal, but these devices may need direct liquid cooling over constrained temperature range to perform properly.

We're not really shrinking, but stacking everything. Channels, dies and even power rails. Maybe it's time to think how we manage this thermals. Stacking helps us reducing ~10% ish power uses, but increase density a lot. We'll rely on a liquids...etc for a while, but I think it's time to integrate thermal managements into semiconductor value chains as well, like how we did in packaging..

 

[Tanj]

it's time to integrate thermal managements into semiconductor value chains as well, like how we did in packaging..

Hard to figure out what you mean.

Packaging is integrated thermal management. Logic has had deeply integrated power management for some time, everything from variable clock domains to blocks which can be shut down to FIVR with different Vdd domains. Thinned die, liquid immersion, textured or channeled backs is just the evolution of packaging.

Was there some other aspect you are referring to?

Vertical packaging can improve efficiency, so in applications like mobile it can make sense even if thermal impedance rises, the drain on battery and heat transfer to user will decline due to efficiency, and those chips are not running hot enough to limit the circuits, it is more about burning the user skin. Servers are where the heat really comes, the heat removal has been deeply engineered for years, and stacking die is tough to reconcile with the thermals.

 

[semiman]

Hard to figure out what you mean.

I was thinking about some micro-channel based ideas. Create small channels inside of the interposer to allow coolants directly into interposers or cold plates. I think i've seen it some IBM materials I think. Since these ideas require additional wafer processing, these could be foundries job like they're doing in packaging(We used to think packaging as wires and molds, but now we also know there are Si interposers...etc).

 

[Tanj]

Create small channels inside of the interposer to allow coolants directly into interposers or cold plates.

Yes, that is the most extreme variant. But the microchannels are not in the interposer, they are etched into the back of the chip, in designs for beyond 1kW/cm2. Think of "microfins on the backside" in flowing fluid and you are up to hundreds of watts. I don't think these are ready for prime time yet because viscosity rises, unless you try something exotic like critical CO2 as the fluid. Folks are still working on heat-sinke shapes that balance viscosity while getting laminar flow and avoiding deadpools. And if materials are used with higher thermal conductivity the design needs to avoid creating mechanical stress on the silicon due to thermal expansion differences.

My hunch is that BSPD is going to open up a whole new willingness to engineer shapes into the backside, and server farms are already several years into investigating and preparing for coolants to be circulating through packages. So long as the transition from primitive cold-plates to more advanced and integrated back-plates can work with similar outside-the-package plumbing and fluids the adoption will be fast.

 

[Mirko Vukovic]

Yes, that is the most extreme variant. But the microchannels are not in the interposer, they are etched into the back of the chip, in designs for beyond 1kW/cm2. Think of "microfins on the backside" in flowing fluid and you are up to hundreds of watts. I don't think these are ready for prime time yet because viscosity rises, unless you try something exotic like critical CO2 as the fluid. Folks are still working on heat-sinke shapes that balance viscosity while getting laminar flow and avoiding deadpools. And if materials are used with higher thermal conductivity the design needs to avoid creating mechanical stress on the silicon due to thermal expansion differences.

My hunch is that BSPD is going to open up a whole new willingness to engineer shapes into the backside, and server farms are already several years into investigating and preparing for coolants to be circulating through packages. So long as the transition from primitive cold-plates to more advanced and integrated back-plates can work with similar outside-the-package plumbing and fluids the adoption will be fast.

Regarding microchannels, take a look at Corintis from Lausanne/Switzerland

 

[Tanj]

Yep, a good one.

Look at how similar their channels designs are to what you might do with the "giant" levels of backside copper power distribution. You could build that with criss-cross metal layers by using a sacrificial layer where you would normally have had insulator.

The trick is to match the pressure, flow rates, and fluids to the infrastructure in a data center. It will happen.

 

[hist78]

It's really hard to summarize complex technological decisions into single word. Intel decided to wait for EUV methologies and throughput to increase, while using drastic new measures(COAG, Cobalt metals...etc), to increase densities using DUV. So Intel was risk taker of transistor manufacturing, but somwehat conservative of equipment(only in litho, since they used cobalt equip)

Now it's reversed. Intel decided to use High NA first, then adopt schemes one by one. Intel started production of Foveros in 2018, but now in mass production, showing that they're waiting for a maturity.

TSMC started EUV risk production in 2017 and N7+ high volume production with EUV in 2019. On the other hand Intel started EUV risk production in the late 2023 through 2024. Intel is about 4 to 6 years late than TSMC in adopting EUV. I believe it's caused by multiple issues in addition to the maturity of the EUV technology.

Intel's decision was influenced by financial considerations, management priority, and its visions (or lack of vision).

Intel spent precious time and cash doing acquisition, paying dividends, and share buyback. From 2016 to 2019, Intel had decent "Operating Cash Flow" but ended up with negative or a small "Net Cash Flow". Intel didn't have additional financial strength as people assumed in investing in their core production capability. It seems to me that Intel leadership back then believed that higher Intel stock price (through dividends and share repurchase) and external acquisition are more critical. Once Intel leadership decided the spending priority, not buying EUV tools due to its maturity is just a good excuse to support their decision.

From 2016 to 2019 while TSMC was busy buying EUV machines, Intel spent US$28.45 billion on external acquisition, US$27.34 billion on stock buyback, and US$21.12 billion on dividends. The stock buyback and paying dividends especially had very limited impact on Intel's ability to design and to manufacture the best semiconductor products.

Intel Mobileye 2022 revenue was merely $1.87 billion. If we look back this Intel 2017 acquisition, it seems too costly. It not only drained $15.3 billion cash out of Intel but also deprived the available resources at a critical moment from other important areas such as EUV, AI, GPU, advanced packaging, and possible mobile.

Was TSMC, AMD, or Nvidia purely lucky to make those right decisions that led to their success today? Or Intel blew it?


Data source: https://stockanalysis.com/stocks/intc/financials/cash-flow-statement/

 

[hist78]

Talking about Moboileye, it just announced a bad news today:

"We currently expect Q1 revenue to be down approximately 50%, as compared to the $458 million revenue generated in the first quarter of 2023. We also currently believe that revenue over the balance of the year will be impacted by inventory drawdowns to a much lesser extent."

Mobileye Releases Preliminary FY2023 Financial Results and Initial 2024 Outlook

Mobileye Global Inc. (Nasdaq: MBLY) (“Mobileye”) today releases preliminary FY2023 results and a preliminary financial outlook for FY2024. FY2023 and

www.businesswire.com

 

[Tanj]

Was TSMC, AMD, or Nvidia purely lucky to make those right decisions that led to their success today? Or Intel blew it?

Intel 10nm should have been feasible without EUV, broadly equivalent to TSMC n7 which did not use EUV and yielded fine. Whatever went wrong with it was not inherently due to deferring EUV. And bear in mind they had EUV machines for research and had done for years, so they understood them. Lack of EUV is a red herring.

Whatever went wrong with Intel 10 seriously derailed them. I hope eventually it gets published for business and tech leaders to study, since it was not just a tech problem but a management fiasco. The "copy exact" model and the failure to yield after committing to production probably means they screwed up every line intended for the new node. My dealings with their x64 architects and planners at the time, and the general chaos of their product introductions up through 2021, indicated that they did not effectively communicate the problem nor project the consequences in such a way as to allow the product groups to change plans and work around it. They just kept "+++" patching both the process and the product line.

My estimate is they had a non-lithography technical problem vastly magnified by management who could not or did not properly assess the consequences and take effective action. Especially as we now see beautiful nodes like N4 in production with a host of leading edge improvements that show they never lost technical capability to build a process, nor did they lack understanding of how to do advanced litho. The blame seems squarely on management. If there is any justification for C-suite remuneration it should be their ability to assess problems swiftly and pull everyone together on the right course. 3 years delay in the road map was not deserving a passing grade.

 

[nghanayem]

Intel 10nm should have been feasible without EUV

It was feasible, hence why it works now. It just took a lot more work to get their than intel expected it to.

broadly equivalent to TSMC n7 which did not use EUV and yielded fine. Whatever went wrong with it was not inherently due to deferring EUV. And bear in mind they had EUV machines for research and had done for years, so they understood them. Lack of EUV is a red herring.

That is an overly simplistic view. 10nm and N7 are VERY different processes. Just looking from a litho perspective TSMC used SALELE for everything except fin patterning which was SAPQ. Intel for it's part used SAPQ for fins but also for M1/M0. SAPQ is more complex than SALELE (just like how SALELE is far more complex than direct print) especially for something that isn't super easy to do cuts for like fins. Given my limited understanding of litho EPE and alignment across mask layers, I would guess that the jump to SAPQ could be exponentially harder than the jump to SAPD (but that is getting into Fred Chen territory so I won't talk out of my rear about it). When talking about intel 4, intel said they made two major improvements beyond EUV for the BEOL. For one they said they were only going to do vias on a grid. They also changed the pitch gearing so that they didn't need to have the mirrored versions of cells interspersed in the design. They claimed that these changes drastically reduced the number of configurations/LLEs, slightly lowered maximum chip density, and improved performance and yield. To my knowledge N7 uses both girded interconnects and it doesn't have weird pitch gearing. How much if any impact these had to 10nm's schedule I couldn't tell you even if I did know. But my point is there are lots of differences beyond the pitch difference.

technical problem vastly magnified by management who could not or did not properly assess the consequences and take effective action. Especially as we now see beautiful nodes like N4 in production with a host of leading edge improvements that show they never lost technical capability to build a process, nor did they lack understanding of how to do advanced litho. The blame seems squarely on management. If there is any justification for C-suite remuneration it should be their ability to assess problems swiftly and pull everyone together on the right course. 3 years delay in the road map was not deserving a passing grade.

Based on the revolving door of CEOs, the former QCOM CTO in charge of the arch team and TD getting the boot for Ann leading an independent TD, and interviews from Ann about "what went wrong" seem to agree with your theory that management made whatever technical issues there were even worse. Ann also said to Ian C that inflexibility and a lack of contingencies for aggressive targets was also an issue.