Wow. It is mostly not like 30k full wafers, but it could be 30k wafer-step in Hi NA EUV machine. If it is 1k wafer per day, then the tool/tools have been up-running quite well. It is amazing.
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Intel was too early with EUV in the 2010s. I hope they're right about it now.Wow. It is mostly not like 30k full wafers, but it could be 30k wafer-step in Hi NA EUV machine. If it is 1k wafer per day, then the tool/tools have been up-running quite well. It is amazing.
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I assume the article writer butchered the order of words and that they meant that 18A would be used to develop high-NA. This would be consistent with prior statements from Ann Kehleher and Mark Phillips that high-NA would be debugged on 18A. This could be like TSMC debugging immersion on 90nm before inserting it for its first commercial use at 40nm, or it could be like TSMC's limited productization of N7+ to derisk 2020's N6 and N5. I suspect which option depends on high-NA maturity. If things are very smooth then why not make a fully productized 18A-highNA derivative people can use if they want to and have 14A use more high-NA layers. If things are just okay keep that 18A derivative as a purely internal development vehicle and have 14A do a conservative high-NA insertion. And if things make a sudden and unexpected turn for the worst you can just use the original low-NA only 14A process that Intel showed off at IFS-DC 2024."Intel has said it plans to use the high NA machines to help develop what it calls its 18A manufacturing technology, which is scheduled for mass production with a new generation of PC chip later this year.
It has said it plans to put the high NA machines into full production with its next generation of manufacturing technology called 14A, but has not given a mass production date for that technology."
Is this correct? Intel is using HNA-EUV to develop 18A?
30000 wafers/qtrAt a conference in San Jose, California, Intel senior principal engineer Steve Carson said Intel has produced 30,000 wafers, the large discs of silicon that can yield thousands of computing chips, in a single quarter with ASML's high numerical aperture (NA) lithography machines.
10K WSPM still a decent number30000 wafers/qtr
This should be a general new generation vs older generation thing. 3800 model should be similar improvement over older models.However, Carson said ASML's new high NA machines are about twice as reliable as the earlier generation in initial testing.
It's likely (or hopefully) not used most of that time.10K WSPM still a decent number
Yeah but we still don't know about the test chipsIt's likely (or hopefully) not used most of that time.
If the "earlier" machines are the previous EUV NA, he might be talking about ~ 20 nm pitch.The new ASML machines, which print features onto chips using beams of light, can also do the same work as earlier machines using fewer exposures, saving time and money.
Carson said early results at Intel's factories showed that the high NA machines can do what took earlier machines three exposures and about 40 processing steps with just one exposure and a "single digit" number of processing steps.
100% correct.I assume the article writer butchered the order of words and that they meant that 18A would be used to develop high-NA. This would be consistent with prior statements from Ann Kehleher and Mark Phillips that high-NA would be debugged on 18A. This could be like TSMC debugging immersion on 90nm before inserting it for its first commercial use at 40nm, or it could be like TSMC's limited productization of N7+ to derisk 2020's N6 and N5. I suspect which option depends on high-NA maturity. If things are very smooth then why not make a fully productized 18A-highNA derivative people can use if they want to and have 14A use more high-NA layers. If things are just okay keep that 18A derivative as a purely internal development vehicle and have 14A do a conservative high-NA insertion. And if things make a sudden and unexpected turn for the worst you can just use the original low-NA only 14A process that Intel showed off at IFS-DC 2024.