Intel Manufacturing Business Suffers Setback as Broadcom 18A Tests Disappoint

[Artificer60]

Was Intel 20A planned as a foundry offering and not an internal only node?

I thought Intel’s strategy was 4 for internal, 3 for foundry + internal, 20A for internal, and 18A for foundry+internal?

No, 20A was never planned as a foundry offering. Patrick Gelsinger's original plan shoehorned it in to run some small portion of the Arrow Lake volume. Intel wisely decided to save the cost of ramping that volume IMO. 20A did its job, which was to provide the process learning necessary to get to 18A.

 

[siliconbruh999]

They also cancelled Arrow lake refresh cost savings

 

[Fred Chen]

Was Intel 20A planned as a foundry offering and not an internal only node?

I thought Intel’s strategy was 4 for internal, 3 for foundry + internal, 20A for internal, and 18A for foundry+internal?

Qualcomm was announced as a customer in 2021: https://www.theverge.com/2021/7/26/22595002/intel-qualcomm-chips-foundry-services-amazon-aws-20a but nothing came of it. As discussed here https://semiwiki.com/forum/index.ph...-a-potential-takeover.21046/page-3#post-75227 there were PDK problems and the agreement was apparently not binding. Qualcomm also had TSMC and even Samsung as foundry partners. So this should count as a first foundry mishap.

 

[Xebec]

Qualcomm was announced as a customer in 2021: https://www.theverge.com/2021/7/26/22595002/intel-qualcomm-chips-foundry-services-amazon-aws-20a but nothing came of it. As discussed here https://semiwiki.com/forum/index.ph...-a-potential-takeover.21046/page-3#post-75227 there were PDK problems and the agreement was apparently not binding. Qualcomm also had TSMC and even Samsung as foundry partners. So this should count as a first foundry mishap.

Thanks Fred - I’m just questioning the validity of the article if 20A was never intended for external customers. I guess exceptions are possible, but..

 

[nghanayem]

18A wasn't on the roadmap back then. The 5N4Y in July 2021 was 10nm SF, i7, i4, i3, and 20A. Dollars to donuts if 18A was announced back then that slide would have said 18A. Granted we are being pedantic because 20A and 18A are the same base node and the names are completely arbitrary.

 

[Xebec]

18A wasn't on the roadmap back then. The 5N4Y in July 2021 was 10nm SF, i7, i4, i3, and 20A. Dollars to donuts if 18A was announced back then that slide would have said 18A. Granted we are being pedantic because 20A and 18A are the same base node and the names are completely arbitrary.

Intel's Process Roadmap to 2025: with 4nm, 3nm, 20A and 18A?!

www.anandtech.com

Fwiw article from July 2021 showing 18A

(Agreed the naming is silly. If you looked at SRAM scaling TSMC N3 is "TSMC 3%" . Not defending Intels math, just having fun).

 

[MKWVentures]

18A wasn't on the roadmap back then. The 5N4Y in July 2021 was 10nm SF, i7, i4, i3, and 20A. Dollars to donuts if 18A was announced back then that slide would have said 18A. Granted we are being pedantic because 20A and 18A are the same base node and the names are completely arbitrary.

This is true.... 18A wasnt on initial discussions before July 21.

But Intel did separate them for last 3 years and did repeatedly say Arrow lake and 20A is where BSP and GAA are demonstrated. but 20A Arrow lake was cancelled due to Fab economics (as it should have been)

This is why it is so unfortunate that Pat continues to tell stories about what will be years from now. Intel delivered products. Intel did not deliver 20A. those are facts
Pat said in an interview years ago that "granite lake was not delayed [from 4 to 3]... it was "enhanced" ..... OK if you say so.

Lets focus on what Intel actually ramps, whether fabs are being tooled out, and Finances. technology does not always lead to financial strength (20A showed this). Hopefully Intel has a plan to ramp 18A somewhere without losing 2 billion on it in 2025.

 

[count]

Fab economics are not going to magically get better with 18A instead of 20A. If they can't get a lot of high volume products on 18A it will be a money loser.

 

[Jure]

From what we know, Intel plans to have lots of internal volume on 18A: CWF, Panther Lake, Diamond Rapids, even some Xe3 tiles should be on 18A. We'll see how external volume goes. I would rather say that they may be limited by how fast they can ramp. The latter will undoubtedly be very expensive. Intel will have to buy more and latest EUV machines in addition to high NA EUV for 14A. If fabs can actually become profitable in 27/28 while ramping 14A, this would be quite an achievement.

Given that performance and density improvements have become rather limited (look at Intel's projections for 14A), 18A might be a very good process even in 2030, so it will be a long time near the leading edge. Imo, 18A has the potential to be very profitable later on, but Intel must take care of design tools and PDK.

 

[OneEng]

From what we know, Intel plans to have lots of internal volume on 18A: CWF, Panther Lake, Diamond Rapids, even some Xe3 tiles should be on 18A. We'll see how external volume goes. I would rather say that they may be limited by how fast they can ramp. The latter will undoubtedly be very expensive. Intel will have to buy more and latest EUV machines in addition to high NA EUV for 14A. If fabs can actually become profitable in 27/28 while ramping 14A, this would be quite an achievement.

Given that performance and density improvements have become rather limited (look at Intel's projections for 14A), 18A might be a very good process even in 2030, so it will be a long time near the leading edge. Imo, 18A has the potential to be very profitable later on, but Intel must take care of design tools and PDK.

Considering the trials and tribulations that Samsung had with GAA (and I don't believe that they had BSPD in their process), what time frame do you (or others) see 18A CWF being produced (in volume)? My guess is that it will likely be late in 2025, and that would also likely mean that Intel will not be producing 18A for external customers until 2026 (I could be wrong on this one).

Regardless, 18A appears to have density and power characteristics roughly in line with TSMC's N3. By 2025, I think the leading node at TSMC will be N2 which I believe will have performance characteristics that are notably better than N3 and 18A. If all of this is true, then Intel would find itself selling its very expensive 18A at a discount. A discount determined by how TSMC is pricing N3 in 2025 .... while TSMC can move its premium pricing to its N2 node.

I guess what I am saying is that while Intel 3 was a welcome breath of fresh air out of the Intel foundry, it still looks like Intel has more than a year of rough financial times ahead of it.

 

[Daniel Nenni]

• “Broadcom completed the successful bring-up of Industry’s first Face-to-Face 3D SoIC in September 2024. This device uses TSMC’s 5nm Process, 3D die-stacking and CoWoS® packaging technologies to integrate 9x die(s) and 6x HBM stacks in a large package. This paves the way for a number of 3D-SoIC production ramps expected in 2025. Broadcom continues to use 3Dblox which is a welcome advancement for interoperability of EDA tools in 3D IC design flow.” – Greg Dix, vice president, R&D & Engineering, ASIC Product Division, Broadcom

 

[kevin01]

• “Broadcom completed the successful bring-up of Industry’s first Face-to-Face 3D SoIC in September 2024. This device uses TSMC’s 5nm Process, 3D die-stacking and CoWoS® packaging technologies to integrate 9x die(s) and 6x HBM stacks in a large package. This paves the way for a number of 3D-SoIC production ramps expected in 2025. Broadcom continues to use 3Dblox which is a welcome advancement for interoperability of EDA tools in 3D IC design flow.” – Greg Dix, vice president, R&D & Engineering, ASIC Product Division, Broadcom

Intel seems to see itself leading over TSMC in the area of advanced packaging, but I have never seen news of high volume chip makers (such as Nvidia, Broadcom) using IFS packaging. I wonder why.

 

[Jure]

Considering the trials and tribulations that Samsung had with GAA (and I don't believe that they had BSPD in their process), what time frame do you (or others) see 18A CWF being produced (in volume)? My guess is that it will likely be late in 2025, and that would also likely mean that Intel will not be producing 18A for external customers until 2026 (I could be wrong on this one).

No idea about real volume production (I don't have any insider info). You can either trust Pat or not.

Regardless, 18A appears to have density and power characteristics roughly in line with TSMC's N3. By 2025, I think the leading node at TSMC will be N2 which I believe will have performance characteristics that are notably better than N3 and 18A. If all of this is true, then Intel would find itself selling its very expensive 18A at a discount. A discount determined by how TSMC is pricing N3 in 2025 .... while TSMC can move its premium pricing to its N2 node.

From what we now, N2 is supposed to be much better on power than N3, but not so much performance wise (anandtech). I believe that 18A (or 18AP) will be comparable to N2 performance wise, much better cost wise and worse on power and density. The purpose of backside power delivery is to relax metal pitches and reduce EUV usage -> reduce costs. N2 has no backside power and looks denser than N3B and N3B is supposedly already a quite complex and expensive process.

 

[Daniel Nenni]

No idea about real volume production (I don't have any insider info). You can either trust Pat or not.

From what we now, N2 is supposed to be much better on power than N3, but not so much performance wise (anandtech). I believe that 18A (or 18AP) will be comparable to N2 performance wise, much better cost wise and worse on power and density. The purpose of backside power delivery is to relax metal pitches and reduce EUV usage -> reduce costs. N2 has no backside power and looks denser than N3B and N3B is supposedly already a quite complex and expensive process.

Low double digit performance increases is normal for TSMC nodes. The performance increase between N3 and N2 are comparable to N5 and N3. Remember, TSMC does incremental optimizations based on customer collaboration. Power is a big deal now for data centers, especially here in the US with our outdated power grids. So TSMC mobile and AI customers are stressing on power. You also have to look at density and at N3 that involves DTCO:

Semiconductor design is not cut and dry anymore which is why working closely with a wide range of customers is key, unless of course you don't have customers....

 

[kevin01]

View attachment 2319

Low double digit performance increases is normal for TSMC nodes. The performance increase between N3 and N2 are comparable to N5 and N3. Remember, TSMC does incremental optimizations based on customer collaboration. Power is a big deal now for data centers, especially here in the US with our outdated power grids. So TSMC mobile and AI customers are stressing on power. You also have to look at density and at N3 that involves DTCO:

View attachment 2320

Semiconductor design is not cut and dry anymore which is why working closely with a wide range of customers is key, unless of course you don't have customers....

I remeber TSMC renamed some node to N2, so that it sounds a better match of 18A, naming wise

 

[OneEng]

No idea about real volume production (I don't have any insider info). You can either trust Pat or not.

From what we now, N2 is supposed to be much better on power than N3, but not so much performance wise (anandtech). I believe that 18A (or 18AP) will be comparable to N2 performance wise, much better cost wise and worse on power and density. The purpose of backside power delivery is to relax metal pitches and reduce EUV usage -> reduce costs. N2 has no backside power and looks denser than N3B and N3B is supposedly already a quite complex and expensive process.

It is interesting to me that BSPD reduces process complexity. I had assumed that it provided process performance improvements in power handling allowing higher transistor densities within a lower power envelope. Of course, I made this assumption in a complete engineering vacuum.

From a competitive perspective, I think that Intel is going to have a tough time meeting TSMC's price points even if 18A is less expensive in time and processes to N2 simply because TSMC will have its N2 lines 100% booked while Intel is still creating market. TSMC will have a big economy of scale advantage.

It is my understanding that N3E and N3P are less complex than N3B (that Intel is using). I believe that this was specifically done to reduce process complexity and process cost.

 

[ChrisGar]

Intel seems to see itself leading over TSMC in the area of advanced packaging, but I have never seen news of high volume chip makers (such as Nvidia, Broadcom) using IFS packaging. I wonder why.

It was widely reported a few months ago that Nvidia was exploring Intel specifically just for packaging. (driven by potential TSMC packaging supply limits) As always, neither side said anything official.

 

[Daniel Nenni]

I remeber TSMC renamed some node to N2, so that it sounds a better match of 18A, naming wise

It will be a little confusing with Intel 18A and 14A versus TSMC A16 and A12. TSMC may have done that on purpose to poke at Intel. CC Wei has a very competitive sense of humor.

It reminds me of back when TSMC called their first FinFET node 16nm versus Intel 14nm because Morris Chang felt Intel 14nm was ahead technically. Samsung then called theirs 14nm even though it was comparable to TSMC 16nm. TSMC then had to explain the differences to customers which was not fun.

 

[Daniel Nenni]

It was widely reported a few months ago that Nvidia was exploring Intel specifically just for packaging. (driven by potential TSMC packaging supply limits) As always, neither side said anything official.

I remember when Pat said they had over 100 customer engagements or something about significant customer interest for IFS. That set the expectations very high and there is no where to go but down from there. I do see IFS packaging as a business opportunity but TSMC has the home court advantage and they are increasing packaging capacity at a very high rate, something like doubling this year and next year. TSMC will only package TSMC die so Intel Foundry and Samsung Foundry die are not welcome.

Personally I am rooting for Intel Foundry as is everybody I know, even TSMC. I just think they need to pivot and not go head-to-head with TSMC otherwise Pat Gelsinger will lose his head.

 

[hist78]

It will be a little confusing with Intel 18A and 14A versus TSMC A16 and A12. TSMC may have done that on purpose to poke at Intel. CC Wei has a very competitive sense of humor.

It reminds me of back when TSMC called their first FinFET node 16nm versus Intel 14nm because Morris Chang felt Intel 14nm was ahead technically. Samsung then called theirs 14nm even though it was comparable to TSMC 16nm. TSMC then had to explain the differences to customers which was not fun.

I don't understand why TSMC chose the names A16 and A12 for its nodes. They are identical to Apple's A16 and A12 SoC names.

One day, we might see an Apple A20 on TSMC's A16 node, or an A22 on A12. It's confusing!