Yes, Pat said Intel would beat TSMC and then he retired unexpectedly. Had Pat said Intel would beat Samsung Foundry he may not have retired unexpectedly.
If anything, Pat was pushed out because his 5-year turnaround strategy wasn't completed in 3 years. And if rumors are true, he was pushed out for not having a competitive AI roadmap. Which I guess checks out with intel canceling Falcon Shores just after he retired.
What about BK? He had so much Intel manufacturing and operations experience?
He hated working in the fabs and spent 80% of his career licking boots in Santa Clara instead of managing his fabs (at least, so I'm told).
He got fired as well and it was not due to his failed mobile strategy
His mobile push didn't get him pushed out, but it did get a lot of people laid off to recoup the cost and not all of it was in design like it should have been for a design screw up like that.
How are employees motived by lies, pipe dreams,
What pipe dream? 18A is the most advanced process in the whole world in production and will be the first/only 2nm process with products in the market this year. Ann told Pat that was the moonshoot she thought she could hit when Pat asked her what she could do with a blank check, and by all indications intel has done it. They once again are leading and based on A14 being in production in 2028 (and by extension products being in 2029) then Intel's lead only seems to be growing larger if intel continues with their 2 yr cadence of new cpus on new process nodes as Pat and Tan have both committed.
and massive layoffs? We call it drinking the Corporate Kool-Aide and Intel is famous for it.
While yes that is demoralizing. Intel having poor market estimates and corporate planning isn't mutually exclusive with 5N4Y being a motivator.
Lip-Bu is not famous for it so get ready for change.
Lip-Bu is laying off average joes just like Pat. And I have seen no indication it will just be management getting the axe. After all, he has already made the product side less organized, added more administrative burden to teams. Like a dedicated AI organization that is pseudo separate from DCAI and reports to DCAI and him directly. Doesn't exactly scream simplifying management layers and letting the technical folks do their jobs to me.
This is the problem with Intel in a nutshell. Do you know how CC Wei knows that N3 is competitive with 18A? Because his customers told him so after evaluating the PDK. Do you not think that customers were part of his internal assessment? He cannot say that of course but I have been told the same. I'm sure Lip-Bu already knows this because he listens to customers.
That's the thing he said N3P should be comparable. TSMC is many things, humility when it comes to comparisons with other manufactures or their tool vendors has never been one of them. Even if we disregard that trend, it just makes sense to say your product is better rather than comparable if it is even 1% better. If your product is losing by a bit good marketing will always call themselves "competitive", and if you are even 1% better in any metric people say they are superior. After all, TSMC to this day claims their 16FF has/had better PPA than SF14, yet TSMC's density was like 2-4% worse for the A series SOC and their performance was like 0-2% better. They also tried to sell their 20nm as "comparable" to intel 22nm and their real i22nm competitor 16FF as most of the way as good as intel 14nm when it was around as far behind as intel 4/3 is to N2. Now granted for mobile I'm sure N3P is better than 18A, but for HPC TSMC doesn't have a winner until N2 at best.
But sure, 18A is the best and don't worry about TSMC N2 even though it has more design starts than N3 which was uncontested. Hopefully Lip-Bu cuts everyone at Intel who thinks this way otherwise I see little hope of a turnaround. Sorry to be so blunt but I really want to see Intel succeed.
You can have the best technology and not have more design wins than TSMC... Look at Intel custom foundry when they were sitting around 4 years ahead, and a whole lot of nothing other than tiny FPGA wins resulted from that. From my observations technology is like number 4 or 5 on the priority list of fabless customers (after trust to deliver wafers, trust the wafers will be delivered to spec, trust the wafers arrive when expected, and then maybe design ease of use). You also speak as if Intel hasn't won a single design win from a fabless chip vendor on leading edge processes. Intel could unironically be making 10A wafers today, and they would still have to go through the small trust building contract stage. NOBODY will go all in on an untested foundry with no/negative track record. At least someone like Samsung is a known quantity and has been doing this for around 20 years.
I am bit of confused here is 18A that bad or it is that PDK is horrible that customer can't get proper PPA out of it.
Besides the fact that many people were already doing N2 design work before Pat even became CEO, the problem IMO is that the PDK is later than it would be for typical foundry rollout. 18A is making products in high volumes now, and foundry risk production only started this year. TSMC started their risk production and PDK 1.0 last year and they aren't even launching Apple products (aka virtual IDM relationship) until next year. Even at foundry direct they mentioned that performance on 18A was a few % below the final target. TSMC N2 performance would have been around that level when Fab12 transferred the process to the HVM fab to finish development back last year. As an IDM not a big deal to be working on performance at the 11th hour since Intel products runs respins all the time because they basically don't do pre Si validation, so making late process tweaks for more performance isn't a big deal or a major inconvenience to anyone. For a foundry customer, they won't start designing their final chip until that process is locked down with no more major changes (see NVIDIA on 40nm for what happens when the process/PDK isn't properly locked down before design start). For this reason, TSMC focuses on getting their performance architecture done first so that they can get the transistor models and process flow locked down as early as possible. That way designers can get to work ASAP and accelerate their TTM. Of course this comes at the expense of early yield as the development resources are less focused on running experiments to improve DD as well as new performance vintages inevitably destabilizing the process/raising DD. Once the performance is at that 95% level, you can get the rest of the way on variation reduction and small tweaks that are transparent to designers. Since you aren't doing these big performance revisions to the transistor or spending limited development resources on performance enhancements, you can then see a rapid reduction in DD and catch up to the guy who is doing performance and yield enhancements at the same time. Intel has admitted that what would go on to become 18A wasn't fully defined with foundry in mind because they weren't a foundry when the early pathfinding and process definition was happening, and that 14A was the first process that was informed by learnings from prior customer collaborations on 18A, i3, and MediaTek on i16. Considering that Intel has the major IP vendors on 14A done like 3-4 quarters after Intel announced that stuff being done on 18A and the process is coming out 2 years after 18A, it would seem to point to Intel 14A ecosystem being ready at a more normal time relative to the HVM date (ie before HVM start rather than at/after HVM start).
Just like Intel said Pat retired.