You are currently viewing SemiWiki as a guest which gives you limited access to the site. To view blog comments and experience other SemiWiki features you must be a registered member. Registration is fast, simple, and absolutely free so please, join our community today!
Intel 3 was not much of a lithographic challenge compared to Intel 4.
M2 and M4 got pitch reduced, from 45 nm to 42 nm. Interestingly, the 210 nm cell height then becomes five 42 nm pitch M2 tracks. 21 ML Intel 3 got M11-M15 pitches reduced (to 98 nm to 160 nm range).
Intel 3 was not much of a lithographic challenge compared to Intel 4.
M2 and M4 got pitch reduced, from 45 nm to 42 nm. Interestingly, the 210 nm cell height then becomes five 42 nm pitch M2 tracks. 21 ML Intel 3 got M11-M15 pitches reduced (to 98 nm to 160 nm range). View attachment 2033
If Intel '3' is supposed to mean comparable to TSMC N3, it doesn't seem appropriate. This looks like node renaming a la Samsung, just to make 5N4Y seem achieved.
Intel 3 was not much of a lithographic challenge compared to Intel 4.
M2 and M4 got pitch reduced, from 45 nm to 42 nm. Interestingly, the 210 nm cell height then becomes five 42 nm pitch M2 tracks. 21 ML Intel 3 got M11-M15 pitches reduced (to 98 nm to 160 nm range). View attachment 2033
Just to check - are we comparing HP vs HP variations or HP vs HD? I understand at least one variation of TSMC N3 is a lot more relaxed (“closer to N5 density”) than other N3 variants for example.
Just to check - are we comparing HP vs HP variations or HP vs HD? I understand at least one variation of TSMC N3 is a lot more relaxed (“closer to N5 density”) than other N3 variants for example.
Pitches I'm comparing Intel 3 to are N3P, already relaxed in some cases compared to original Apple-only N3.
Minimum metal pitch is nothing to do with HP or HD libraries, these are different numbers of fins and metal tracks (cell height), and sometimes small differences in CPP (a few nm).
Basically Intel 3 has wider tracks with bigger spacing than TSMC N3; this can give higher speed, but certainly has lower density, so it's really not a comparable process in the "nm race" -- Intel 3 is much closer to TSMC N5.
(and don't forget that every single one of these processes -- "7nm" or "5nm" or "4nm" or "3nm" -- will have the same minimum physical gate length of around 16nm which is the FinFET limit...)
At the ISS conference held from April 4th through 6th I presented on who I thought would have the leading logic technology in 2025. The following is a write up of that presentation. ISS was a virtual conference in 2021 and I presented on who currently had logic leadership and declared TSMC the...
semiwiki.com
According to Scotten Jones in April 2022, Intel 3 was to be slightly (<10%) denser than TSMC N5, but Intel 3 has higher transistor performance than TSMC N3.
(Interesting also that Samsung 3nm is listed as less dense than either Intel 3 or TSMC N5).
At the ISS conference held from April 4th through 6th I presented on who I thought would have the leading logic technology in 2025. The following is a write up of that presentation. ISS was a virtual conference in 2021 and I presented on who currently had logic leadership and declared TSMC the...
semiwiki.com
According to Scotten Jones in April 2022, Intel 3 was to be slightly (<10%) denser than TSMC N5, but Intel 3 has higher transistor performance than TSMC N3.
(Interesting also that Samsung 3nm is listed as less dense than either Intel 3 or TSMC N5).
Looking at those Intel metal pitches above -- yes, in terms of MP and presumably CPP. Gate density is also a function of cell height/drive strength; Intel tend to focus on HP libraries (e.g. 3-fin) which are also lower density but suit their CPU products, TSMC focus more on HD libraries (e.g. 2-fin) which are higher density (and typically used for gates/mm2 metrics) and suit more of their customers -- but they also have HP libraries for HPC customers who need higher speed and are less worried about power and density.
At the VLSI Technology Symposium this week Intel released details on their i3 process. Over the last four nodes Intel has had an interesting process progression. In 2019, 10nm finally entered production with both high performance and high-density standard cells. 10nm went through several...
Looking at those Intel metal pitches above -- yes, in terms of MP and presumably CPP. Gate density is also a function of cell height/drive strength; Intel tend to focus on HP libraries (e.g. 3-fin) which are also lower density but suit their CPU products, TSMC focus more on HD libraries (e.g. 2-fin) which are higher density (and typically used for gates/mm2 metrics) and suit more of their customers -- but they also have HP libraries for HPC customers who need higher speed and are less worried about power and density.
www.hardwareluxx.de
