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[h=1]eSilicon, Northwest Logic and SK Hynix create high-bandwidth memory (HBM) hardware demonstration[/h]
I find this announcement lacking in terms of packaging detail and performance numbers. I mean, it's absolutely just a DRAM with a new PHY. Those two elements are the easy ones. The TSV stacking (assumed solved), host to HBM packaging and thermal density are critical, but no information on that.
I wondered what a "human body model" demonstration was before I came her to discover it's nothing to do with ESD.
This is a 2.5D interposer based design. So the logic chip (here an FPGA) is not under the memory but off to the side. The memories are stacked with TSV just like the Micron/IBM hybrid memory cube (HMC). My understanding is that thermal density is not a big problem with stacked DRAM, there just isn't enough power being dissipated to be a major problem. Putting the logic in the same stack (like HMC) can be different, and for sure putting the memory stack on top of a real processor really seals in a lot of power -- IBM server prototypes (or maybe for real) do it the other way up, with the memory on the bottom and the processor on top so that they can put a heat sink on it.
TSV stacking seems to be a solved problem. HMC uses it, and others both announced and unannounced. The remaining TSV issues are mostly whether the cost can be got down. Yes, there are challenges to reducing the exclusion zone around the TSV and also characterizing the effect on transistor thresholds "near" the TSVs. But cost is the big one. For more general stacks, the known-good-die (KGD) problem is also an issue, but for memories where yield can be got up with redundancy, this is less critical.
