user nl
Active member
I was studying a bit the latest openly reported updates on EUV technology as presented by INTEL and ASML at the special EUV sources workshop in Dublin (9-11 Nov 2015), and listening to the investors webcasts from 2 Dec at Scottsdale by ASML CFO Wolfgang Nickl and from Dec 8 at San Francisco by ASML Director Investor Relations Skipp Miller. All the links are at the end of this post.
My take from this all:
1) solid progress is made during 2015, it seems ASML reached all their targets.
2) there are indeed 3 NXE3350 (the newest model) shipped this year. Skipp said you may hear a few snippets of its first performance at SPIE2016 end of February, but probably not a whole lot. It takes a while to get the machine tuned-up and collect solid data on wafers. Probably more during Q2 or mid 16. However, he said you'll probably hear less and less on that from the customers as they are working on their EUV process development and EUV HVM insertion.
3) Skipp also clearly said INTEL is now fully working on process development using EUV for the 7 nm node, while TSMC is working fully on mid-node 10 nm insertion of 1 or 2 layers. He didn't say much about Samsung's EUV insertion strategy.
4) From the Dublin meeting slides of INTEL's Britt Turkot one can see various tests at INTEL on wafers/day and runs at 80 Watt source power. There was good improvement made in the droplet generator, and it is clear the source power of the field installed systems can run (much) higher. But probably the collector lifetime reduces too much yet if they would run at say >100 Watt. Data provided in the slides by IBM shows a run from August-end of September at 80 Watt from which a 6 month collector lifetime is estimated. INTEL and TSMC probably want to first get the in situ collector cleaning installed, before they run the source at higher power.
Data is shown that ASML has had in house run the source at 185 Watt for 1 hour at 23% dose overhead. So the source power target of 250 Watt seems already basically done.
The main thing for the INTEL development team is now the availability (they don't need the high source power now) and 4 week runs showing close to 70% results. But this needs to be much higher.
Many more details in the slides on the whole EUV ecosystem and what the status is, also removable pellicles that ASML will start producing in 2016 with coatings that can handle >120 Watt.
5) the targets set by ASML for 2016 are 250 Watt source power, >125 Wafers/hour and >90% availability.
6) for the investors: ASML's CFO 2020 target of 10 BEuro revenue and tripling of earnings (all relative to 2013 earnings of about 1 BEuro) are still standing full in his and Skipp's talks.
The thing now is to start on EUV lithography for nodes beyond 2020 and getting the EUV system to high NA.
Happy Holidays, user nl
2 Dec Scottsdale:
https://cc.talkpoint.com/cred001/120115a_ae/?entity=107_IH2KOY6
8 Dec San Francisco:
https://cc.talkpoint.com/barc002/120815a_ae/?entity=65_8SMC4EN
Dublin, INTEL
http://www.euvlitho.com/2015/S1.pdf
Dublin, ASML
http://www.euvlitho.com/2015/S2.pdf
Dublin complete contributions and links:
http://www.euvlitho.com/2015/2015 Source Workshop Proceedings.pdf
My take from this all:
1) solid progress is made during 2015, it seems ASML reached all their targets.
2) there are indeed 3 NXE3350 (the newest model) shipped this year. Skipp said you may hear a few snippets of its first performance at SPIE2016 end of February, but probably not a whole lot. It takes a while to get the machine tuned-up and collect solid data on wafers. Probably more during Q2 or mid 16. However, he said you'll probably hear less and less on that from the customers as they are working on their EUV process development and EUV HVM insertion.
3) Skipp also clearly said INTEL is now fully working on process development using EUV for the 7 nm node, while TSMC is working fully on mid-node 10 nm insertion of 1 or 2 layers. He didn't say much about Samsung's EUV insertion strategy.
4) From the Dublin meeting slides of INTEL's Britt Turkot one can see various tests at INTEL on wafers/day and runs at 80 Watt source power. There was good improvement made in the droplet generator, and it is clear the source power of the field installed systems can run (much) higher. But probably the collector lifetime reduces too much yet if they would run at say >100 Watt. Data provided in the slides by IBM shows a run from August-end of September at 80 Watt from which a 6 month collector lifetime is estimated. INTEL and TSMC probably want to first get the in situ collector cleaning installed, before they run the source at higher power.
Data is shown that ASML has had in house run the source at 185 Watt for 1 hour at 23% dose overhead. So the source power target of 250 Watt seems already basically done.
The main thing for the INTEL development team is now the availability (they don't need the high source power now) and 4 week runs showing close to 70% results. But this needs to be much higher.
Many more details in the slides on the whole EUV ecosystem and what the status is, also removable pellicles that ASML will start producing in 2016 with coatings that can handle >120 Watt.
5) the targets set by ASML for 2016 are 250 Watt source power, >125 Wafers/hour and >90% availability.
6) for the investors: ASML's CFO 2020 target of 10 BEuro revenue and tripling of earnings (all relative to 2013 earnings of about 1 BEuro) are still standing full in his and Skipp's talks.
The thing now is to start on EUV lithography for nodes beyond 2020 and getting the EUV system to high NA.
Happy Holidays, user nl
2 Dec Scottsdale:
https://cc.talkpoint.com/cred001/120115a_ae/?entity=107_IH2KOY6
8 Dec San Francisco:
https://cc.talkpoint.com/barc002/120815a_ae/?entity=65_8SMC4EN
Dublin, INTEL
http://www.euvlitho.com/2015/S1.pdf
Dublin, ASML
http://www.euvlitho.com/2015/S2.pdf
Dublin complete contributions and links:
http://www.euvlitho.com/2015/2015 Source Workshop Proceedings.pdf
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