This year GSA marks its 20 year anniversary and 20 successful years of industry collaboration. To commemorate the anniversary, GSA is unveiling a video series of interviews with some of the leading minds in the ecosystem discussing the industry and their participation with GSA over the years. The videos feature industry leaders such as Steve Mollenkopf of Qualcomm, Scott McGregor of Broadcom, Mark Edelstone from Morgan Stanley and many more.
They also have 2 technical working group meetings next week that are open for registration. Please find the details listed below:
What: 3DIC Packaging Working Group Meeting
When: Wed, JUL 23, 2014 |2:00 PM – 5:00 PM
Where: PMC-Sierra, 1380 Bordeaux Drive, Sunnyvale, CA, 94089
Why: EDA vendors provide tools to decrease design cycle time and help ensure accuracy. Cadence, Mentor Graphics, and others will present their solutions. The Q3 3DIC Working Group meeting will focus on:
When: Thurs, JUL 24, 2014 | 9:00 AM – 12:00 PM
Where: Synopsys, 700 E. Middlefield Road, Bldg 8, Mountain View, CA, 94043
Why: To ensure IP works properly in any design, testing and validation is critical. In this quarter’s meeting, the working group will hear from Granite River Labs and Teledyne Lecroy on each aspect of ensuring IP interoperability across billions of products. The Q3 IP Working Group meeting will cover:
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They also have 2 technical working group meetings next week that are open for registration. Please find the details listed below:
What: 3DIC Packaging Working Group Meeting
When: Wed, JUL 23, 2014 |2:00 PM – 5:00 PM
Where: PMC-Sierra, 1380 Bordeaux Drive, Sunnyvale, CA, 94089
Why: EDA vendors provide tools to decrease design cycle time and help ensure accuracy. Cadence, Mentor Graphics, and others will present their solutions. The Q3 3DIC Working Group meeting will focus on:
- Cadence 3D-IC Tool Suite, Brandon Wang, Cadence
- Verifying Physical Die-to-Die Alignment and Interconnect in 2.5D and 3D Systems, John Ferguson, Mentor Graphics
- Role of Path Finding?, Bill Martin, E-System Design
- ESD Best Practices
When: Thurs, JUL 24, 2014 | 9:00 AM – 12:00 PM
Where: Synopsys, 700 E. Middlefield Road, Bldg 8, Mountain View, CA, 94043
Why: To ensure IP works properly in any design, testing and validation is critical. In this quarter’s meeting, the working group will hear from Granite River Labs and Teledyne Lecroy on each aspect of ensuring IP interoperability across billions of products. The Q3 IP Working Group meeting will cover:
- TSMC9000[SUP]TM[/SUP] Program Expansion Through Increase of IP Validation Capability and Capacity, Lluis Paris, Granite River Labs
- USB and PCIe Compliance and Test – Planned Success, Kimberly McKay, Product Line Manager – Embedded Instruments, Teledyne Lecroy
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