Gelsinger Opens Up, as Intel Reportedly Expands Orders to TSMC

[fansink]

According to various articles (probably same source), TSMC will be producing Intel CPUs, GPUs, and NPUs tiles for the Arrow and Lunar Lake platforms.

Is this true?
Is this going to affect Nvidia's already strained chip supply?

[News] Gelsinger Opens Up, as Intel Reportedly Expands Orders to TSMC | TrendForce Insights

Pat Gelsinger, CEO of Intel, announced on February 22nd that Intel will expand its orders to TSMC, as per a report by Commercial Times. Following t...

www.trendforce.com

Intel CEO Confirms TSMC's Process Nodes To Power Next-Gen CPUs: N3 For Arrow Lake & N3B For Lunar Lake

Intel CEO confirms the use of TSMC N3 process node for next-gen Arrow Lake & N3B node for its Lunar Lake CPUs launching later this year.

wccftech.com

https://www.chinatimes.com/newspapers/20240223000152-260202?chdtv/

https://www.ctee.com.tw/news/20240223700048-439901/

 

[Tanj]

Is this true?

Yes.

Is this going to affect Nvidia's already strained chip supply?

No. Nvidia is limited by packaging capacity. Intel has its own packaging capacity.

 

[MKWVentures]

I think their might be a little misunderstanding in this .... but let me know
Lunar lake was always planned to be all TSMC. low power, on chip integration
Arrow lake was always planned to do 20A CPU, all other items TSMC. Is this article saying even the CPU on Arrow lake is TSMC?

I was told there are multiple ARL skus and some may be TSMC and some Intel CPU depending on the timing. But I think the initial Arrow lake CPU has to be 20A or Intel had massive roadmap change.... let me know

 

[Daniel Nenni]

It's funny that it said Intel would take TSMC capacity from others including AMD. Not even close. Intel did a prepay for N3 capacity and TSMC built it accordingly. My guess is that Intel will not use all of the wafers they paid TSMC for since business has not been all that great and N3 yield is ahead of schedule.

It takes Intel about 18 months to design a chip so none of this is unexpected. There are no last minute changes. It is all built in the wafer agreements.

TSMC is not the only packaging option for Nvidia. They have other sources. They will always suggest supply constrained so prices can remain high. Nvidia ASPs are at record levels due to the supply constraint and lack of competition. You can bet the big HPC customers are designing their own chips to counter Nvidia, if that is even possible. Exciting times in the semiconductor ecosystem, absolutely!

The Nvidia GTC is next month. Exciting times. Jensen is a great speaker.....

NVIDIA CEO Jensen Huang Keynote at GTC 2025

Experience GTC 2025 In-Person and Online March 17-21, San Jose

www.nvidia.com

 

[fansink]

It's funny that it said Intel would take TSMC capacity from others including AMD. Not even close. Intel did a prepay for N3 capacity and TSMC built it accordingly. My guess is that Intel will not use all of the wafers they paid TSMC for since business has not been all that great and N3 yield is ahead of schedule.

It takes Intel about 18 months to design a chip so none of this is unexpected. There are no last minute changes. It is all built in the wafer agreements.

TSMC is not the only packaging option for Nvidia. They have other sources. They will always suggest supply constrained so prices can remain high. Nvidia ASPs are at record levels due to the supply constraint and lack of competition. You can bet the big HPC customers are designing their own chips to counter Nvidia, if that is even possible. Exciting times in the semiconductor ecosystem, absolutely!

The Nvidia GTC is next month. Exciting times. Jensen is a great speaker.....

NVIDIA CEO Jensen Huang Keynote at GTC 2025

Experience GTC 2025 In-Person and Online March 17-21, San Jose

www.nvidia.com

Thanks Daniel, do you know if TSMC will be producing Intel CPUs, GPUs, and NPUs tiles for both the Arrow and Lunar Lake platforms? MKWVentures mentioned that Intel may be producing one of the CPU's

 

[Daniel Nenni]

Thanks Daniel, do you know if TSMC will be producing Intel CPUs, GPUs, and NPUs tiles for both the Arrow and Lunar Lake platforms? MKWVentures mentioned that Intel may be producing one of the CPU's

They are called chiplets. I refuse to call them tiles!

I do not know anything about specific products and I do not track internal Intel product names so I wouldn't know a Lunar Lake if it hit me in the face.

I was told a while back that Intel would make all CPU chiplets and use TSMC for everything else. I was also told that Intel will use TSMC N3 for low power GPUs. I asked at the event yesterday but I got a non answer. I will check back channels next week.

Intel has to increase internal content in their end products or IFS is doomed. Use our foundry even if we don't? That is a tough sell. I do know that Intel has not inked an agreement with TSMC N2 yet so hopefully that is the switch over to 18A.

 

[fansink]

After the IFS Direct 2024 event Pat Gelsinger, Intels CEO mentioned in a meeting, with the press and analysts that Chipzilla is incorporating TSMC’s advanced process node technology for their CPUs named Arrow Lake and Lunar Lake.

During the discussion, Pat highlighted Intel’s collaboration with TSMC for CPU designs emphasizing that future CPUs like Arrow Lake and Lunar Lake will shift from 5nm to 3nm nodes.

Intel CEO Affirms TSMC’s N3 and N3B Process Nodes for Next-Gen CPUs: Arrow Lake & Lunar Lake

After the IFS Direct 2024 event Pat Gelsinger, Intels CEO mentioned in a meeting, with the press and analysts that Chipzilla is incorporating TSMC's advanced

technosports.co.in

 

[MKWVentures]

After the IFS Direct 2024 event Pat Gelsinger, Intels CEO mentioned in a meeting, with the press and analysts that Chipzilla is incorporating TSMC’s advanced process node technology for their CPUs named Arrow Lake and Lunar Lake.

During the discussion, Pat highlighted Intel’s collaboration with TSMC for CPU designs emphasizing that future CPUs like Arrow Lake and Lunar Lake will shift from 5nm to 3nm nodes.

Intel CEO Affirms TSMC’s N3 and N3B Process Nodes for Next-Gen CPUs: Arrow Lake & Lunar Lake

After the IFS Direct 2024 event Pat Gelsinger, Intels CEO mentioned in a meeting, with the press and analysts that Chipzilla is incorporating TSMC's advanced

technosports.co.in

Belief is still that Arrow lake is 20A CPU with other chiplets made by TSMC (like Meteor Lake). Most of the silicon is TSMC. Lunar lake is believed to be 100% TSMC. There may be Arrow lake SKUs with a different configuration and CPU. TSMC silicon use and Intel purchase revenue from TSMC is increasing very fast. This is all part of the Intel plan and is why Intel is splitting manufacturing out.

 

[Daniel Nenni]

After the IFS Direct 2024 event Pat Gelsinger, Intels CEO mentioned in a meeting, with the press and analysts that Chipzilla is incorporating TSMC’s advanced process node technology for their CPUs named Arrow Lake and Lunar Lake.
During the discussion, Pat highlighted Intel’s collaboration with TSMC for CPU designs emphasizing that future CPUs like Arrow Lake and Lunar Lake will shift from 5nm to 3nm nodes.

Intel CEO Affirms TSMC’s N3 and N3B Process Nodes for Next-Gen CPUs: Arrow Lake & Lunar Lake

After the IFS Direct 2024 event Pat Gelsinger, Intels CEO mentioned in a meeting, with the press and analysts that Chipzilla is incorporating TSMC's advanced

technosports.co.in

I was at that event and I do not remember it that way. I do not recall the author of this article being there either but there were quite a few of us.

Is this going to affect Nvidia's already strained chip supply? No, not at all.

 

[fansink]

I think their might be a little misunderstanding in this .... but let me know
Lunar lake was always planned to be all TSMC. low power, on chip integration
Arrow lake was always planned to do 20A CPU, all other items TSMC. Is this article saying even the CPU on Arrow lake is TSMC?

I was told there are multiple ARL skus and some may be TSMC and some Intel CPU depending on the timing. But I think the initial Arrow lake CPU has to be 20A or Intel had massive roadmap change.... let me know

On another thread, Lefty believes that Arrow Lake CPU will be primarily produced by TSMC, except low-end devices?

I’m trying to establish whether or not Intel’s roadmap is slipping, while Gelsinger is claiming to be on-track to overtaking TSMC.

Perhaps I’m misunderstanding the “overtaking” metric, I had presumed it was technologically, but maybe it’s not even an adverb.

Intel signs Microsoft as foundry customer, says on track to overtake TSMC

Intel signs Microsoft as foundry customer, says on track to overtake TSMC https://finance.yahoo.com/news/intel-expects-overtake-tsmc-making-165037092.html

semiwiki.com

 

[MKWVentures]

On another thread, Lefty believes that Arrow Lake CPU will be primarily produced by TSMC, except low-end devices?

I’m trying to establish whether or not Intel’s roadmap is slipping, while Gelsinger is claiming to be on-track to overtaking TSMC.

Perhaps I’m misunderstanding the “overtaking” metric, I had presumed it was technologically, but maybe it’s not even an adverb.

Intel signs Microsoft as foundry customer, says on track to overtake TSMC

Intel signs Microsoft as foundry customer, says on track to overtake TSMC https://finance.yahoo.com/news/intel-expects-overtake-tsmc-making-165037092.html

semiwiki.com

Overtaking means process leadership. it will be debatably but it means 18A for Pat. Intel will not have 18A production units shipping to end customers in 2024.
Meteor lake and Arrow lake have always been planned to have 4 chiplets, 3 are TSMC. 70% of silicon is TSMC On arrow lake There are options for more cores and a different sku that is RUMORED to MAYBE have TSMC CPU . But the initial Arrow lake SKU is expected to have 20A CPU and 3 TSMC chips and be launched in December 2024.

There seems to be a lot of "quotes" from people reported online that turn out to not be true or are known to know be true as we all heard the actual quote. I am not sure if if this is intentional or if people reporting just dont know definitions like that a CPU is a chiplet on current architectures with 3 other chiplets (IO, GPU, SOC). This will get even wierder when we have have Last level cache as separate chiplets (or even chips)

 

[Fred Chen]

Endgame question: can Intel get/support more 18A customers than TSMC can with N2?

 

[fansink]

Endgame question: can Intel get/support more 18A customers than TSMC can with N2?

Intel will only have a small fraction of EUV tools compared to TSMC, that in itself will be a large barrier?

 

[Daniel Nenni]

Endgame question: can Intel get/support more 18A customers than TSMC can with N2?

No, not even close. I highly doubt CC Wei will let Intel get the process lead. A paper lead maybe but not when it comes to customer silicon. N2 will be another big node for TSMC, absolutely.

 

[hist78]

No, not even close. I highly doubt CC Wei will let Intel get the process lead. A paper lead maybe but not when it comes to customer silicon. N2 will be another big node for TSMC, absolutely.

Are those paper/specs lead still meaningful? Every semiconductor company decided their implementation based on a lot of factors such as power, performance, area, cost, IPs, competition, capacity, time to market, or customers' preference, etc. What's good for a particular Apple's chip might not be that important for Intel, AMD, Qualcomm, or Nvidia, and vice versa.

 

[Fred Chen]

Intel will only have a small fraction of EUV tools compared to TSMC, that in itself will be a large barrier?

I wonder how much confidence Intel has to do this?

 

[nghanayem]

Intel will only have a small fraction of EUV tools compared to TSMC, that in itself will be a large barrier?

Irrelevant. TSMC is not converting any of their N5 or N3 fabs into N2 fabs. Intel AZ and TSMC's two N2 sites are both starting from a grand total of zero steppers. And before you say it, ASML doesn't play favorites. All firms (and not just intel and TSMC) will have equal access to the queue.

Endgame question: can Intel get/support more 18A customers than TSMC can with N2?

I doubt IFS has the bandwidth to support hundreds of customers at this time. Also if I am being honest I don't think anyone can have more customers than TSMC on a given node bar TSMC having a fumble of intel 10nm proportions (and even then, it may need to be even worse than that). Intel could have intel 45nm HKMG vs strainless TSMC 65nm levels of technological advantage, and the majority of the leading foundry customers would still put most of their volume on TSMC. They simply have too much momentum for any advantage 18A might have to cause a coup.

Maybe, and this is a BIG maybe, by 14A or 10A they can have more wafer volume (not customers) than TSMC if you count internal. But with intel's main product lines being all disaggregated now, I don't know/think that intel can take their bleeding edge scale back from TSMC even if intel went back to having a CPU monopoly. As an example take MTL. The SOC is like 20-30% intel 4 by area (as opposed to something like ADL mobile where the intel 7 die is like 90% of the package). As a result intel only needs like 1/5th to 1/4th the wafer starts to get the dies for the same number of units sold. Disag lowering the capex demands from intel BUs and offering ability to milk nodes for longer is of course great for the finances, but it absolutely destroys the scale that intel's BUs used to offer (a late 2020 techinsights estimates was that intel 10nm capacity was 80-90% of TSMC's total N5 capacity).

TLDR if intel wants to recapture the scale advantage they have enjoyed for many decades prior, IFS needs to hit it out of the park. Additionally intel needs to get their bleeding edge products back from TSMC once the current contracts are fulfilled, and intel prod co needs to gain MSS back from basically every fabless firm. Technically, it is possible. But it is not something I would bet my home on.

The one thing that can greatly screw up the math is how disag happens with TSMC's customers, as that could make intel taking the scale advantage back much more likely. Right now folks like MTK, Apple, QCOM, and NVIDIA only make monolithic dies. If TSMC's major customers start disaggregating their products, then TSMC will also lose a lot of scale on their most advanced process. Losing most of their intel business will of course also shift the math further in intel's favor.

 

[benb]

I look at 5 nodes 4 years as a statement of Intel R&D performance, not manufacturing. Samsung and TSMC could well be doing the same thing, just less public about it, and most likely are. But as Elon Musk says "Manufacturing is hard". Samsung yields have consistently struggled going from R&D to manufacturing. Intel has struggled with 10nm for 5 years (!!). Only TSMC seems to have the skill to go seamlessly from R&D to manufacturing, at scale.

If Gelsinger had a catchphrase for "now we get how to go from R&D to manufacturing" I would look at this as a strategic inflection point in the industry. Possibly, Foundry products will be easier to make. Potentially, chiplets are easier to make. Giant AI chip packages could change things in Intel's favor. But manufacturing is hard, until the products actually arrive, and are torn down, and we see what TSMC vs. Intel content are in them, I wouldn't disagree if someone pointed out, actually, IDM 2.0 and Fab-Lite are pretty much the same thing, only with smoke and mirrors.

 

[lefty]

In a quote from the original article Gelsinger says that Arrow lake will be 100% TSMC, including the CPU tile:

Gelsinger announced the goal of becoming the world's second largest wafer foundry in 2030, and announced that two generations of CPU Tile will be produced using TSMC's N3B process and will provide process nodes to some competitors.

This seems to contradict Intel's offical road map:

Gelsinger also confirmed the expansion of orders to TSMC, confirming that TSMC will hold orders for Intel's Arrow and Lunar Lake CPU, GPU, and NPU chips this year, and will produce them using the N3B process, officially ushering in the Intel notebook platform that the outside world has been waiting for for many years. CPU orders. According to Intel's product roadmap, Arrow lake will use Intel 20A, Lunar lake will be 18A, and will be equipped with PowerVia and RibbonFET transistor designs.

this is link to google translation:

基辛格鬆口 擴大下單台積電 - 財經要聞

台積電創辦人張忠謀眼中最注意的對手－英特爾（INTEL）執行長基辛格22日首度鬆口，英特爾將擴大下單台積電，將2024年全新推出的二大次世代平台Arrow lake、Lunar lake之CPU Tile（晶片塊）交由台積電生產製造。基辛

www-chinatimes-com.translate.goog

 

[Daniel Nenni]

Gelsinger also confirmed the expansion of orders to TSMC, confirming that TSMC will hold orders for Intel's Arrow and Lunar Lake CPU, GPU, and NPU chips this year, and will produce them using the N3B process, officially ushering in the Intel notebook platform that the outside world has been waiting for for many years. CPU orders. According to Intel's product roadmap, Arrow lake will use Intel 20A, Lunar lake will be 18A, and will be equipped with PowerVia and RibbonFET transistor designs.

TSMC N3B process?