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Question about etching in advanced node (7nm and beyond)
In every news, it is always mentioned that the problem during scaling is in the lithography process.
The equipment and techniques are so expensive,they become prohibitive for manufacturers, and other discussion related to these.
my question:
1. if lithography were not a problem (in advanced node), does it mean that we can always do etching as long as the resist developed nicely?
2. if the answer of Q1 is no, what are the problems in etching in advanced node?
This question has many answers. The first is that suppose we could project clean EUV, there are still problems with the interaction between the EUV and the resist. The EUV energy is currently around 94 eV (about 1.5e-17 J) per photon. This means that a limited number of photons occur (at dosage of 50 mJ per sq cm, that is 5e-14 J (around 3,300 photons) per 10nm square. Stochastic variation affects the edges. Then the photons trigger ionization events with electrons that scatter and produce secondary effects several nm away from the original event. These are two ways that perfect lithographic projection does not make a perfect pattern.
Next, the resist is developed. This mechanism will generally amplify the effects (a 10 nm cube may have hundreds of thousands of molecules, while only 1% or so were directly affected) of the radiation and that may result in additional distortions. The projection may have spread more or less at depth creating side profiles to worry about.
Finally, once the resist is developed it will need to resist the etch. I believe most etching at these dimensions uses plasma (but others here may correct me) and is fairly directional. Even so, it must have some directional drift and scatter which will add to the noise (as Portland summarizes), especially if the etch must be relatively deep.
All of these areas of chemistry and physics are research topics around the world.
Like you, I would be curious to know the numerical contributions from each effect. I suspect these are trade secrets, though.
my question:
1. if lithography were not a problem (in advanced node), does it mean that we can always do etching as long as the resist developed nicely?
2. if the answer of Q1 is no, what are the problems in etching in advanced node?
For 3D NAND the lithography is relatively easy, no EUV needed, probably ever.
The etch is extremely hard with very high aspect ratios.
The channel hole etch is on its way from 30 minutes per wafer to 60 minutes per wafer!
For all leading edge processes there are etch challenges with selectivity, uniformity, control and high aspect ratios. New techniques like atomic layer etching are getting a lot of attention.
Even Applied Materials management is throwing up their hands and spending $600M on a new META materials development lab in NY. They seem to believe new materials developed there will help not only advanced but older nodes. So perhaps there is plenty of new work to be done but since existing processes were ok no one bothered.
Last August Allen Rasafar (GF) wrote that 7-nm "was quite a learning experience". He also noted that "There are many challenges, from DFM to Metrology, tool, to process tuning." Please do not forget that Metrology was on that list. Please look at the publications describing the use of SCM and SSRM for carrier profiling which are still the two tools used for this purpose. These papers show that SCM has a resolution of 10-nm and SSRM has a resolution of 20-nm. Does it make any sense to use them at the 7-nm node? If EUV enables fabrication at nodes where you cannot do effective fault localization and failure analysis, then why make what you cannot "see"?
