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eASIC files for an IPO

Daniel Payne

Moderator
I'm encouraged to see a semiconductor company file for an IPO, it's been awhile since we've seen much IPO action.

Press Release

View attachment 13357

eASIC Nextreme-3™ is eASIC’s fourth generation eASIC Platform manufactured on a 28 nm CMOS process. The eASIC Nextreme-3 family provides ASIC-like performance, power and low unit-cost combined with FPGA-like design flow and rapid delivery of prototype devices. eASIC Nextreme-3 Platforms come with an enhanced architecture that offers twice the performance and half of the power consumption of eASIC Nextreme-2™ (eASIC’s 45 nm Platforms).

Key Features

  • TSMC 28nm HP process with core operating voltage of 0.85 V
  • Up to 80% lower power than FPGAs
  • Up to twice the performance of 28 nm FPGAs
  • Instant on – No SRAM cells for configuration avoiding SEU CRAM
  • Up to 1.8M eCELLS (18M equivalent ASIC gates)
  • Up to 56 Mbits of embedded memory blocks (bRAMS) with Built-In-Self Repair
  • 800 MHz fine grained 9K bits memory blocks
  • Embedded one bit fast adders for high-speed arithmetic and DSP functions
  • Multi-gigabit I/O with speeds up to 12.5 Gbps
  • New enhanced clocking structure with 36 global clock trees
  • GreenPowerVia disables power to unused logic
  • Support for 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.35 V and 1.2 V IO standards
  • eFUSE for traceability and storing special keys
  • Temperature sensing diode
  • FPGA like design tools and flow
 
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