DVCon is the premier conference on the application of languages, tools and methodologies for the design and verification of electronic systems and integrated circuits. Below are links to slides and posters from DVCon 2013:
Session 1
1.1 - Systematic Application of UCIS to Improve the Automation on Verification Closure
1.2 - UCIS Applications: Improving Verification Productivity, Simulation Throughput, and Coverage Closure Process
1.3 -
Session 2
2.1 - Overcoming AXI Asynchronous Bridge Verification Challenges with AXI Assertion-Based Verification IP (ABVIP) and Formal Datapath Scoreboards
2.2 - Memory Subsystem Verification: Can it be Taken for Granted?
2.3 - How to Succeed Against Increasing Pressure - Automated Techniques for Unburdening Verification Engineers
Session 3
3.1 - How to Kill 4 Birds with 1 Stone: In a Highly Configurable Design Using Formal to Validate Legal Configurations, Find Design Bugs, and Improve Testbench and Software Specifications
3.2 - Using Formal Verification to Exhaustively Verify SoC Assemblies
3.3 - Qualification of Formal Properties for Productive Automotive Microcontroller Verification
Poster Session
1P.1 -
1P.2 - Can You Even Debug a 200M+ Gate Design?
1P.3 - Migrating to UVM: Conquering Legacy
1P.4 -
1P.6 -
1P.7 - Using Formal Techniques to Verify SoC Reset Schemes
1P.8 - Deploying Parameterized Interface with UVM
1P.9 - Unifying Hardware Assisted Verification and Validation using UVM and Emulation
1P.10 - Real Number Modeling: How to Verify Mixed Signal Behavior using Event-Based Simulation
1P.11 - Low-Power Verification Automation – A Practical Approach
1P.12 - Register Verification: Do We Have Reliable Specification?
1P.13 - Switch the Gears of the UVM Register Package to Cruise through the Street Named “Register Verification”
1P.14 - Traffic Profiling and Performance Instrumentation for On-Chip Interconnects
1P.15 - Boosting Simulation Performance of UVM Registers in High Performance Systems
1P.16 - The Need for Speed: Understanding Design Factors That Make Multi-Core Parallel Simulations Efficient
1P.17 - An Approach for Faster Compilation of Complex Verification Environment: The USB3.0 Experience
1P.18 -
1P.19 - Pragmatic Verification Reuse in a Vertical World
1P.20 - Verifying Functionality is Simply Not Enough!
1P.21 - Taming the Beast: A Smart Generation of Design Attributes (Parameters) for Verification Closure using Specman
1P.22 - ASIC-Strength Verification in a Fast-Moving FPGA World
1P.23 - A SystemVerilog Framework for Easy Method Advice in Object-Oriented Test Benches
1P.24 - Run-Time Configuration of a Verification Environment – A Novel Use of the OVM/UVM Analysis Pattern
1P.25 - Maximize Vertical Reuse, Building Module to System Verification Environments with UVM e
1P.26 - Unconstrained UVM SystemVerilog Performance
Session 4
4.1 - Using UVM - The Condensed Guide for Designers, Debuggers, Test-Writers, and Other Skeptics
4.2 - Best Practices in Verification Planning
4.3 - Who’s Watching the Watchmen? The Time has Come to Objectively Measure the Quality of Your Verification Environment
4.4 - Using Advanced OOP Concepts to Integrate Templatized Algorithms & Standard Protocols with UVM
Session 5
5.1 - Mixed-Abstraction Modeling Approach for Hardware-Firmware Co-Design and Functional Co-Verification with Fault Injection of an Automotive Airbag System on Chip Product
5.2 - Lessons from the Field – IP/SoC Integration Techniques Which Work
5.3 - Bringing Constrained Random into SoC SW-Driven Verification
5.4 - Boost Verification Results by Bridging the Hardware/Software Testbench Gap
Session 6
6.1 - Weathering the Verification Storm:Methodology Enhancements used on a Next Generation Weather Satellite C&DH Program
6.2 - I'm Still In Love With My X! (But, do I Want My X to be an Optimist, a Pessimist, or Eliminated?)
6.3 - FSIM_Logic – A VHDL Type for Testing of FLYTRAP
6.4 - Sequence, Sequence on the Wall – Who’s the Fairest of Them All? Using SystemVerilog UVM Sequences for Fun and Profit
Session 7
7.1 -
7.2 - A Tale of Two Languages: SystemVerilog and SystemC
7.3 - Practical Issues in Implementing Fast and Accurate SystemC-Constructed Virtual Platform Simulation
Session 8
8.1 - The Finer Points of UVM: Tasting Tips for the Connoisseur
8.2 - Beyond UVM: Creating Truly Reusable Protocol Layering
8.3 - OVM to UVM: The Definitive Guide
Session 9
9.1 - A Systematic Approach to Power State Table (PST) Debugging
9.2 - Power Aware Verification Strategy for SoCs
9.3 - MS-SoC Best Practices – Advanced Modeling and Verification Techniques for First-Pass Success
Session 10
10.1 - Guaranteed Vertical Reuse – C Execution in a UVM Environment
10.2 - Design and Verification of an Image Processing CPU using UVM
10.3 - Extendable Messaging Techniques for Debugging and Analyzing UVM Testbench Structure and Transaction Flow
Session 11
11.1 - One Compile to Rule Them All: An Elegant Solution for OVM/UVM Testbench Topologies
11.2 - SVA Encapsulation in UVM - Enabling Phase and Configuration Aware Assertions
11.3 - C Through UVM: Effectively using C-Bbased Models with UVM-Based Verification IP
Session 12
12.1 - New and Active Ways to Bind to Your Design
12.2 - Easy Steps Towards Virtual Prototyping using the SystemVerilog DPI
12.3 - Verifying Layered Protocols – Leveraging Advanced UVM Capabilities
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Session 1
1.1 - Systematic Application of UCIS to Improve the Automation on Verification Closure
1.2 - UCIS Applications: Improving Verification Productivity, Simulation Throughput, and Coverage Closure Process
1.3 -
Session 2
2.1 - Overcoming AXI Asynchronous Bridge Verification Challenges with AXI Assertion-Based Verification IP (ABVIP) and Formal Datapath Scoreboards
2.2 - Memory Subsystem Verification: Can it be Taken for Granted?
2.3 - How to Succeed Against Increasing Pressure - Automated Techniques for Unburdening Verification Engineers
Session 3
3.1 - How to Kill 4 Birds with 1 Stone: In a Highly Configurable Design Using Formal to Validate Legal Configurations, Find Design Bugs, and Improve Testbench and Software Specifications
3.2 - Using Formal Verification to Exhaustively Verify SoC Assemblies
3.3 - Qualification of Formal Properties for Productive Automotive Microcontroller Verification
Poster Session
1P.1 -
1P.2 - Can You Even Debug a 200M+ Gate Design?
1P.3 - Migrating to UVM: Conquering Legacy
1P.4 -
1P.6 -
1P.7 - Using Formal Techniques to Verify SoC Reset Schemes
1P.8 - Deploying Parameterized Interface with UVM
1P.9 - Unifying Hardware Assisted Verification and Validation using UVM and Emulation
1P.10 - Real Number Modeling: How to Verify Mixed Signal Behavior using Event-Based Simulation
1P.11 - Low-Power Verification Automation – A Practical Approach
1P.12 - Register Verification: Do We Have Reliable Specification?
1P.13 - Switch the Gears of the UVM Register Package to Cruise through the Street Named “Register Verification”
1P.14 - Traffic Profiling and Performance Instrumentation for On-Chip Interconnects
1P.15 - Boosting Simulation Performance of UVM Registers in High Performance Systems
1P.16 - The Need for Speed: Understanding Design Factors That Make Multi-Core Parallel Simulations Efficient
1P.17 - An Approach for Faster Compilation of Complex Verification Environment: The USB3.0 Experience
1P.18 -
1P.19 - Pragmatic Verification Reuse in a Vertical World
1P.20 - Verifying Functionality is Simply Not Enough!
1P.21 - Taming the Beast: A Smart Generation of Design Attributes (Parameters) for Verification Closure using Specman
1P.22 - ASIC-Strength Verification in a Fast-Moving FPGA World
1P.23 - A SystemVerilog Framework for Easy Method Advice in Object-Oriented Test Benches
1P.24 - Run-Time Configuration of a Verification Environment – A Novel Use of the OVM/UVM Analysis Pattern
1P.25 - Maximize Vertical Reuse, Building Module to System Verification Environments with UVM e
1P.26 - Unconstrained UVM SystemVerilog Performance
Session 4
4.1 - Using UVM - The Condensed Guide for Designers, Debuggers, Test-Writers, and Other Skeptics
4.2 - Best Practices in Verification Planning
4.3 - Who’s Watching the Watchmen? The Time has Come to Objectively Measure the Quality of Your Verification Environment
4.4 - Using Advanced OOP Concepts to Integrate Templatized Algorithms & Standard Protocols with UVM
Session 5
5.1 - Mixed-Abstraction Modeling Approach for Hardware-Firmware Co-Design and Functional Co-Verification with Fault Injection of an Automotive Airbag System on Chip Product
5.2 - Lessons from the Field – IP/SoC Integration Techniques Which Work
5.3 - Bringing Constrained Random into SoC SW-Driven Verification
5.4 - Boost Verification Results by Bridging the Hardware/Software Testbench Gap
Session 6
6.1 - Weathering the Verification Storm:Methodology Enhancements used on a Next Generation Weather Satellite C&DH Program
6.2 - I'm Still In Love With My X! (But, do I Want My X to be an Optimist, a Pessimist, or Eliminated?)
6.3 - FSIM_Logic – A VHDL Type for Testing of FLYTRAP
6.4 - Sequence, Sequence on the Wall – Who’s the Fairest of Them All? Using SystemVerilog UVM Sequences for Fun and Profit
Session 7
7.1 -
7.2 - A Tale of Two Languages: SystemVerilog and SystemC
7.3 - Practical Issues in Implementing Fast and Accurate SystemC-Constructed Virtual Platform Simulation
Session 8
8.1 - The Finer Points of UVM: Tasting Tips for the Connoisseur
8.2 - Beyond UVM: Creating Truly Reusable Protocol Layering
8.3 - OVM to UVM: The Definitive Guide
Session 9
9.1 - A Systematic Approach to Power State Table (PST) Debugging
9.2 - Power Aware Verification Strategy for SoCs
9.3 - MS-SoC Best Practices – Advanced Modeling and Verification Techniques for First-Pass Success
Session 10
10.1 - Guaranteed Vertical Reuse – C Execution in a UVM Environment
10.2 - Design and Verification of an Image Processing CPU using UVM
10.3 - Extendable Messaging Techniques for Debugging and Analyzing UVM Testbench Structure and Transaction Flow
Session 11
11.1 - One Compile to Rule Them All: An Elegant Solution for OVM/UVM Testbench Topologies
11.2 - SVA Encapsulation in UVM - Enabling Phase and Configuration Aware Assertions
11.3 - C Through UVM: Effectively using C-Bbased Models with UVM-Based Verification IP
Session 12
12.1 - New and Active Ways to Bind to Your Design
12.2 - Easy Steps Towards Virtual Prototyping using the SystemVerilog DPI
12.3 - Verifying Layered Protocols – Leveraging Advanced UVM Capabilities
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