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DeepSeek, Huawei, Export Controls, and the Future of the U.S.-China AI Race

KevinK

Well-known member
A long read but the basic synopsis:

* DeepSeek has done some very innovative, but predictable and well-documented things to drive efficient inference. Their innovations are likely to benefit US companies more than DeepSeek as long as China is computation-limited.

“All of DeepSeek’s innovations were algorithmic and architectural. DeepSeek appears to have described all or nearly all of them in great detail in its research papers. That means that U.S. AI labs are free to apply these same innovations in training and deploying their own AI models. Indeed, U.S. firms are already doing so.

But while DeepSeek’s algorithmic innovations are replicable by U.S. firms, DeepSeek will struggle to replicate U.S. AI chip and compute advantages. In the absence of extreme ultraviolet lithography (EUV) technology, China’s most advanced AI chip designer and logic chip manufacturer, Huawei and SMIC, respectively, will most likely remain stuck at 7 nanometers (nm) or perhaps a flawed 5 nm technology node for many years. The CEO of ASML, which is the sole firm in the world manufacturing EUV lithography machines, said “By banning the export of EUV, China will lag 10 to 15 years behind the West. That really has an effect.”

* SMIC and Huawei are definitely having difficulties producing AI chips.


Government officials told CSIS that TSMC manufactured more than 2 million Ascend 910B logic dies and that all of these are now with Huawei. If true, this is enough dies to make 1 million Ascend 910C units. However, the advanced packaging process by which two Ascend 910B dies and HBM are combined into a unified Ascend 910C chip also introduces defects that can compromise the functionality of the chip. Industry sources told CSIS that roughly 75 percent of the Ascend 910Cs currently survive the advanced packaging process.

In December 2024, industry sources told CSIS that SMIC currently has enough immersion deep ultraviolet (DUV) lithography equipment supplied by the Dutch company ASML to produce 85,000 FinFET wafers per month (WPM) across both SN1 (which focuses on 14 nm node production) and SN2 (which focuses on 7 nm and 5 nm production). This acquisition of lithography tools reportedly took effect before Dutch DUV lithography export controls went into effect in mid-2023.

However, the bottleneck in expanding 7 nm (which in SMIC’s node naming system is called “N+2”) production capacity has not been lithography but rather U.S. tools for etching, deposition, inspection, and metrology. The shortage of inspection and metrology tools has also been an important factor preventing SMIC from improving its yield. SMIC acquired lithography equipment as a stockpiling measure in anticipation of future export controls by the Dutch government.

Based on the Ascend 910B die size of 665.61 mm², CSIS estimates that each 300-millimeter diameter silicon wafer produces roughly 80 chip dies. This is simply counting the number of small rectangles (chip dies) that can fit inside the large circle (the wafer). A source told CSIS that of these 80 chip dies:

  • Roughly 20 percent (~16) are fully functional with either no defects or no defects that negatively impact performance. This is the same as saying that SMIC has 20 percent yield when making these chips.
  • An unknown share of chips are functional with degraded performance, though customer demand for such degraded chips (in Huawei’s case, though not Nvidia’s) is low.
  • An unknown share of chips are completely nonfunctional.
However, a February 24, 2025 report by the Financial Times, citing two anonymous individuals, claims that SMIC’s AI chip yield has increased to roughly 40 percent. Industry sources told CSIS that the Financial Times report is not correct and that Huawei/SMIC’s true yield remains at 20 percent. One explanation for the discrepancy would be if the Financial Times’ sources were mistakenly including both the fully functional chips and the chips that are functional but with degraded performance when estimating yield.

 
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