Current multi-patterning techniques (TSMC, Intel, Samsung, GF)

[Fred Chen]

This year’s IEDM showcased a wide range of 7nm processes. First, the IBM alliance including GlobalFoundries and Samsung showed an integration of SADP (self-aligned double patterning) for gates, SAQP (self-aligned quadruple patterning) for fins and EUV for metallization (minimum pitch=36 nm). They showed the logic behind their choices with the graph below:
View attachment 22941

EUV still has some ways to go to become a legitimate successor to immersion. The EUV light collector has a lifetime of months currently, far less than mainstream immersion tools. The power requirement must address increasing shot noise issues (EUV Shot Noise Impact on 7nm) and printable defects can arise from surface contamination without any pellicle and even from buried defects only 0.5-0.6 nm high[1]. Although EUV holds promise for printing 2D patterns it is actually handicapped by horizontal-vertical differences across the illumination slit below 100 nm pitch[2]. Finally, resist outgassing is a problem that is still being studied[3].

LELE pitch-splitting: the earliest multi-patterning

Largely due to these unresolved EUV difficulties, multi-patterning techniques have emerged in leading edge and even maturing technologies. The 20/16/14nm nodes all have a minimum pitch down to around 60 nm. Since the minimum resolvable pitch for immersion lithography is around 80 nm, a 60 nm pitch layout is split into two interleaving sub-layouts, each of 120 nm pitch. In this “pitch-splitting”, every pair of features is divided among two masks. The two masks cannot expose the same resist layer, as the second exposure would wash out the first. Instead, after the first mask is exposed, the layer underneath is etched, then a second resist layer is coated for the second mask to expose. This is followed by a second etch. Due to this flow, it is often called LELE for “Litho-Etch-Litho-Etch”. As expected, the overlay between the two mask exposures is extremely critical.

The 10nm/7nm nodes all appear to have pitches that go down to around 40 nm. Actually this was confirmed in the case of TSMC’s 7nm, also shown at this year's IEDM. TSMC was able to do this with pitch-splitting. Their paper indicated two metal line sets, A and B, whose resistance distributions were then compared. This implies two exposure definitions (LELE). On the other hand, it could also be patterned by SADP (to be discussed below).

SADP/SAQP

SADP is actually very popular among makers of Flash and DRAM memory. The process involves depositing a layer over pre-patterned features, then etching them back to leave only portions on the sidewall called spacers. The spacer pitch is half the pre-patterned feature pitch. A graphic description can be found on Wikipedia here:File:Spacer Patterning.JPG - Wikimedia Commons

SADP does have the advantage of less sensitivity to overlay, but on the other hand, it depends on good spacer width control, as well as good dimensional control of the feature supporting the spacer, usually called the mandrel or core. Moreover, the spacer always forms a loop. To avoid metal loops, at least one additional mask is needed to cut the loop.

However, if the spacer is used to pattern the inter-metal dielectric, then loop or line cutting is not necessary, but a mask may be needed for broader “trimming”. Also, there will be two groups of metal, one defined before the spacer, the other defined after. Unless a uniform spacing between lines is enforced in the layout, metal layouts using this approach can't be fully self-aligned; at least one edge is likely to be exposure-defined. Thus, when the spacer defines the metal edge only in some areas, it's not truly self-aligned double patterning. For a layout with fully uniform inter-metal spacing, it would be possible to use only one immersion exposure. As shown in the picture below (taken from Wikipedia), one set of metal of one color would be defined before spacer from the core/mandrel litho, the other after spacer, without any direct litho definition. But I would consider this a special SADP case. There is still a concern about excess capacitance with this wiring arrangement.

View attachment 18825

Two successive SADPs constitute SAQP, as it allows the pitch to be quartered from two successive halvings. This is what Intel uses for its 10nm. Intel announced their 10nm design rules at their Technology and Manufacturing Day (Intel's Manufacturing Day Materials). Minimum metal pitch is 36 nm, while gate pitch is 54 nm and fin pitch is 34 nm. For SAQP the trenches for metal are in between the final spacers. SAQP layers are generally designed to be lines of comparable length.

If TSMC uses SADP at 7nm, it is unlikely that the spacers are defining the metal linewidths. There can't be any A/B assignment as mentioned above if all metal lines were defined from the same spacer width. On the other hand, the spacer may be used to define the intermetal dielectric width, as mentioned above. This is the so-called "Spacer-is-Dielectric" (SID) style of SADP. The core feature supporting the spacer defines one set of metal, while the remaining metal is defined by gaps between spacers.

Samsung and Triple Patterning

Samsung has reported its use of bi-directional triple patterning for its 10nm (Samsung Starts Industry’s First Mass Production of System-on-Chip with 10-Nanometer FinFET Technology – Samsung Global Newsroom). There are two kinds of triple patterning. There is “LELELE”, which is the natural extension of LELE with a third exposure, and SATP (self-aligned triple patterning), which uses a bi-layer spacer with the two spacer layers etched separately [4], so that the final pitch is one-third the original core pitch. LELELE is more likely to be bi-directional than SATP. More recently, Samsung announced its 10LPU (Samsung Expands its Advanced Foundry Offerings with 14LPU and 10LPU Processes – Samsung Global Newsroom). Possibly, they pushed LELELE to a smaller pitch.

Which one to use?

Actually the different patterning techniques shown by the three companies beg a cost comparison. For sure LELE is cheaper than LELELE. SADP could have the same mask exposure cost as LELE if only one cut or trim mask were used, but it has an extra spacer deposition and etch and core removal step. However, it may be difficult to avoid a 3rd LE, for example, if one line has a break while the adjacent line doesn't. In that case, the broken line must have one color before the break and another color after the break. The adjacent unbroken line gets the third color, corresponding to the 3rd LE. So it looks like a choice between LELELE and SADP. TSMC had two sets of metal, so they likely did not use LELELE. Another possibility is LELE alternating lines with 1-2 additional exposures for line cuts. But LELE, compared to SADP, uses an extra litho
(mask) to define alternating lines, and that is not so attractive.

What is next?

The final thought of course is what next? It is helpful to refer to the IBM alliance graph earlier. To scale a full node down from ~40 nm pitch requires ~28 nm pitch capability; a full node beyond that requires ~20 nm pitch capability. This is beyond the current EUV single exposure capability, as seen in the above graph from the IBM alliance. A high-NA EUV tool might appear after 2020 but its development has only just started recently with the ASML-Zeiss JV (ZEISS and ASML strengthen partnership for next generation of EUV lithography due in early 2020s). Therefore, the current EUV tools would require double patterning for ~28 nm pitch and more patterning than that for ~20 nm pitch. It would obviously be more expensive than TSMC’s 7nm process today. Without EUV, immersion would require quadruple patterning down to 20 nm pitch. SAQP is the most commonly expected choice. However, SAQP using line patterns must avoid numerous cut locations.

References cited:
1. S. Huh, P. Kearney, S. Wurm, F. Goodwin, K. Goldberg, I. Mochi, and E. Gullikson, "Mask Defect Verification Using Actinic Inspection and Defect Mitigation Technology", Proc. of SPIE vol. 7271, 72713J, (c) 2009 SPIE.
2. G. McIntyre, C-S. Koay, M. Burkhardt, H. Mizuno, and O. Wood, "Modeling and Experiments of Non-Telecentric Thick Mask Effects for EUV Lithography", Proc. of SPIE vol. 7271, 72711C, (c) 2009 SPIE.
3. E. Shiobara, Y. Kikuchi, S. Mikami, T. Sasami, T. Kamizono, S. Minegishi, T. Kimoto, T. Fujimori, S. Tanaka, T. Watanabe, T. Harada, H. Kinoshita, "EUV resist outgassing analysis for the new platform resists at EIDEC", Proc. of SPIE vol. 9776, 97762H, (c) 2016 SPIE. Also, reported at: http://ieuvi.org/TWG/Resist/2016/20160221Meeting/07_EIDEC_Shiobara.pdf
4. W. Kang and Y. Chen, "Overlay, Decomposition and Synthesis Methodology for Hybrid Self-Aligned Triple and Negative-tone Double Patterning", Proc. of SPIE vol. 8327, 83270N, (c) 2012 SPIE.

Acknowledgment:
Thanks Daniel Nenni for requesting this topic.

 

[Fred Chen]

Why there can be both double and triple patterning

​As an afterthought, I think it would be safer to add the following comments. Although TSMC has demonstrated 40 nm pitch double patterning, it is surely a unidirectional approach (like SADP). If a customer like ARM wants a bidirectional metal layer, LELELE is still likely to be required to minimize the number of metallization layers. This is due to color conflicts encountered in double patterning. For a multi-patterned layout, feature color can be used to represent the mask it belongs to. An example follows (from Wikipedia). A bidirectional layout will have locations where a line changes tracks, as below:

The existence of the third color (green, representing the third mask exposure) avoids the ambiguity of choosing between red or blue, since using either of those colors would cause two features of the same color to be adjacent, which is forbidden (the neighbor-neighbor pitch is too small for a single mask exposure). It turns out ARM did mention that they support TSMC 7nm but it would require triple patterning: ARM Offers Support For TSMC 7nm Manufacturing | EE Times.

The same layout can still be implemented without triple patterning, if the bend is put in the next connecting metal layer:

So the total number of metallization masks should be considered, rather than merely the number of masks per layer. Of course, the triple patterning can also achieve a tighter pitch than double patterning.

Edit: Wikipedia Multiple Patterning article indicates that LELELE may be replaced by SADP where the spacer is the intermetal dielectric, thus saving a mask while avoiding color conflict:

View attachment 20191

 

[carop]

​Although TSMC has demonstrated 40 nm pitch double patterning by LELE, it is surely a unidirectional approach (like SADP).

Interesting...

Several people from TSMC said they would be using a self-aligned spacer process at 10FF:

In lithography, Cliff Hou said TSMC would push immersion approaches as far as possible, using spacer technology to deliver 40nm metal pitches for 10nm, and double spacer technology to achieve 30nm pitch for 7nm.

Cliff Hou, TSMC VP R and D, on the route to 10nm - and beyond

10FF requires double patterning, but TSMC does not use not the relatively simple litho-etch, litho-etch patterning that is used at 20nm and 16nm. The problem with LELE, BJ Woo said, is that overlay changes can result in variation in the line space. While this is tolerable in 20nm and 16nm, at 10nm this variation will translate into a very small metal space. That can result in an immature dielectric breakdown. Thus, TSMC 10FF uses a self-aligned spacer process that assures that uniform metal line spacings are maintained.

TSMC Symposium: “10nm is Ready for Design Starts at This Moment” - Industry Insights - Cadence Blogs - Cadence Community

 

[Fred Chen]

TSMC "pitch splitting"

Interesting...

Several people from TSMC said they would be using a self-aligned spacer process at 10FF:



Cliff Hou, TSMC VP R and D, on the route to 10nm - and beyond



TSMC Symposium: “10nm is Ready for Design Starts at This Moment” - Industry Insights - Cadence Blogs - Cadence Community

TSMC originally referred to "pitch splitting" as LELE. A consequence of pitch splitting is that the features within a pitch get different colors if they are on different masks. For double patterning, there are two colors. SADP, as applied to gates or fins, does not get coloring since the same spacer patterns all the features. But for metallization, the metal features can still get colored differently if the spacer defines the dielectric between them. So for this spacer-is-dielectric (SID) case of SADP, the metal inside a spacer is one color, while outside it is the other color. So it is still, effectively, pitch splitting.

 

[Fred Chen]

Samsung's 2nd generation 10nm (VLSI Technology 2017)

At the 2017 Symposium on VLSI Technology, Samsung described a "2nd generation" 10nm, which saw the introduction of LELELELE, i.e., four successive mask exposures for the same metal layer.

The extra color and stitching were used to address tight spaces near tips, considering neighboring sides and tips. The obvious difficulties serve as an argument for undirectional, line-cutting layouts, or at least avoiding patterns with hook-like structures.

View attachment 20388

The contact layer remained single exposure and M1 remained triple patterning (LELELE) while Mx was only regular LELE double patterning instead of LELELELE quadruple patterning for the first generation.

As far as scaling benefits goes, it is still quite modest, i.e., half-node. Consequently, a more aggressive technique like SADP or EUV was forecasted for 7nm.


Reference:
W. C. Jeong et al., "10nm 2nd generation BEOL technology with Optimized Illumination and LELELELE," 2017 Symposium on VLSI Technology, T144 (c) 2017 JSAP, under permission of copyright holder.

 

[Fred Chen]

IEDM 2017: Globalfoundries at 7nm and Intel at 10nm

The IEDM 2017 paper by Globalfoundries indicates 7nm metallization uses SADP for MMP of 40 nm, as reported earlier by Scotten Jones (https://www.semiwiki.com/forum/cont...alfoundries-discloses-7nm-process-detail.html). This is 10% looser than the 36 nm pitch shown at last year's IEDM, allowing the use of SADP instead of SAQP or EUV. Fins are of course SAQP, while 56 nm pitch gates were SADP. The company reported developing an SADP process that supported wide metal and vias.

At the same conference, Intel reported MMP of 36 nm for metal 1 and so this layer used SAQP, but interestingly enough, 40 nm pitch metal 0 also got it. Metal 2-4 pitches went up to 44 nm and metal 5 to 52 nm while gate pitch was 54 nm; these all got SADP.

As far as contact/via patterning was concerned, GF indicated those layers were MP-intensive and therefore preferred EUV single patterning. However, the EUV test print results looked more like test patterns, like parts of checkerboard arrays, instead of realistic cell patterns (which are expected to be SAQP-friendly). Intel highlighted its advanced self-aligned patterning for both diffusion and gate contacts. Gate contacts were now moved into the active area, to reduce cell size, hence the name 'Contact over Active Gate.' Not much other detail was given, though.

Also interesting is Intel's switch to cobalt local interconnects. What makes this really interesting, though, is that this cobalt-based interconnect was similarly shown at last year's IEDM by the IBM/GF/Samsung 7nm paper: IEDM 2016 – Setting the Stage for 7/5 nm | Siliconica. It makes one wonder if 36 nm pitch is the cutoff for cobalt insertion.

SAQP is targeted for continuing below 36 nm metal pitch. At these finer pitches, EUV does not have the expected flexibility for 2D patterns. The 32 nm metal pitch has been quite thoroughly studied by ASML, IMEC and others.

Update: selective etching with SAQP looks like the new way to go: https://www.linkedin.com/pulse/feature-selective-etching-saqp-sub-20-nm-patterning-frederick-chen https://www.linkedin.com/pulse/feature-assignments-spacers-saqp-frederick-chen

Papers:

S. Narasimha et al., A 7nm CMOS Technology Platform for Mobile and High Performance Compute Application (c) 2017 IEEE.

C. Auth et al., A 10nm High Performance and Low-Power CMOS Technology Featuring 3rd Generation FinFET Transistors, Self-Aligned Quad Patterning, Contact over Active Gate and Cobalt Local Interconnects (c) 2017 IEEE.

 

[Fred Chen]

ASAP7: a predictive 7nm FinFET PDK

ASAP7 is a 7nm FinFET predictive PDK released by Arizona State University and ARM that is publicly viewable at: ASAP7: A 7-nm finFET predictive process design kit - ScienceDirect

It provides some guidelines for and insights into how advanced patterning would be applied at 7nm.

The gate pitch is 54 nm and is patterned by SADP. The minimum metal pitch is 36 nm but for the SRAM cell, M2 (the 36 nm pitch layer) and M3 are single or continuous straight lines across the cell, making it friendly to SADP or SAQP (i.e., no multiple cut masks). In fact, most published standard cells, especially targeting low tracks, have this same design feature. M1 or any layer used for local interconnection, e.g., M0, would be the only layer that is less patterning-friendly. For this 7nm SRAM, M1 is tied to the gate pitch, so can be patterned by LELE, as also the V1.