Now it's Loogson's 3rd generation. I believe they are using STM 28nm process. Loognson-3 has homogeneous 4 cores. Each core is 64-bit, 4-issue, out-of-order. They use MIPS-like ISA, which is kind of based on MIPS, but has their own optimized instructions.
The Loogson team not only has architecture engineers, IC designers, but also OS, software, PCB designer, even marketing. This means they want to do EVERYTHING literally, except for manufacturing, packaging and testing.
The Loogson project came from a nation fund project. Its 1st generation was 32-bit, single-issue, single core launched in around 2003. Its 2nd generation was 64-bit 4-issue launched in around 2008. (I was in the team from 2003 to 2008. Helped them with high speed custom SRAM and 3rd generation on-chip network development.) Now, they are a company. However, I don't think they are making any money (positive cash flow), because the product is not favored by the market. So they are depending on national fund, and some cooperating projects.
