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CDNLive 2015 - Digital / Advanced Node

Daniel Payne

Daniel Payne

Moderator
The proceedings are online now:

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| width="80%" align="left" valign="top" style="font-family: Arial, Helvetica; background-color: transparent" | [h=6]Session DIG101 : Multi-million Gate Design Challenges at 28nm on PD Flow (PnR, STA)[/h]Einfochips
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| width="80%" align="left" valign="top" style="font-family: Arial, Helvetica; background-color: transparent" | [h=6]Session DIG103 : Challenges and Solutions for 14nm Design Flows[/h]GLOBALFOUNDRIES
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| width="80%" align="left" valign="top" style="font-family: Arial, Helvetica; background-color: transparent" | [h=6]Session DIG105 : Addressing Capacity, Runtime and Co-relation Challenges for 28nm SOC Implementation and Closure[/h]MaxLinear
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| width="80%" align="left" valign="top" style="font-family: Arial, Helvetica; background-color: transparent" | [h=6]Session DIG202 : Maximizing PPA on ARM’s Next Generation High Performance Processor Using the Latest Cadence Implementation and Signoff Tools/Flow[/h]ARM
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| width="80%" align="left" valign="top" style="font-family: Arial, Helvetica; background-color: transparent" | [h=6]Session DIG203 : IEEE1801 EDI Partitioning, Implementation and LP Signoff[/h]Marvell Semiconductor
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| width="80%" align="left" valign="top" style="font-family: Arial, Helvetica; background-color: transparent" | [h=6]Session DIG204 : Accelerating Tapeout Schedules of High Performance Processor Designs Using the Latest Cadence Implementation and Signoff Flow[/h]Freescale Semiconductor
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| width="80%" align="left" valign="top" style="font-family: Arial, Helvetica; background-color: transparent" | [h=6]Session DIG205 : Pushing the Power and Performance Boundaries of Cortex-M for Future Embedded Processor Design[/h]ARM
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| width="80%" align="left" valign="top" style="font-family: Arial, Helvetica; background-color: transparent" | [h=6]Session DIG207 : Pre-route Automation in Encounter Platform – Bus Description Language and Noise Aware Repeater Insertion.[/h]Soft Machines
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