Aldec™ Design and Verification Update February 2014

[Daniel Nenni]

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| For DO-254 Compliance, Hardware Flies Not Simulations
How to increase Verification Coverage by Test
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| Why Digital Design Students choose Active-HDL™
Mixed-language simulation for VHDL-2008, Verilog and SystemVerilog (Design)
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| Still managing FPGA requirements with Word and Excel?
Smart tips for safety-critical applications, like DO-254
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Press Release:

Aldec solves another DO-254 challenge with Requirements Reviewer in
Spec-TRACER™

Events - Aldec:

Fast Track to Riviera-PRO
Part 1: Design Entry and Simulation
Feb. 27 (Webinar, Online)

DVCon 2014
Mar. 3-6 (Industry Event, San Jose, CA)

SystemVerilog Assertion Workshop
Mar. 5 (Training, Japan)

MATLAB/Simulink Co-Verification Workshop
Mar. 14 (Training, Japan)

Fast Track to Riviera-PRO
Part 2: Advanced Debugging,
Code Coverage and Scripting
Mar. 27 (Webinar, Online)

DO-254 Practitioners Course
May 14-16 (Training, Las Vegas, NV)

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