A Verilog simulator comparison

[Daniel Payne]

An anonymous RTL designer just shared his experience comparing ModelSim from Mentor versus CVC from Tachyon.

The full post is here.

 

[kaaliakahn]

Here is one paper that i would recommend.I am currently working with this group.

A new distributed event-driven gate-level HDL simulation by accurate prediction by Dusung Kim, Ciesielski, M. and Seiyang Yang ​

Dept. of Electr. & Comput. Eng., Univ. of Massachusetts, Amherst, MA, USA ​

published in DATE 2011

Its a good one​

 

[Daniel Payne]

Thanks for sharing the paper, the IEEE has a download for this at $10 for members and $31 for non-members.

 

[kaaliakahn]

is there a policy of sharing copyright content on this forum? I can post it but i don't want to be in trouble

 

[Daniel Payne]

If we copy/paste content then we give clear credit to the source. If the source is a paid site, then no, do not copy/paste.

 

[kaaliakahn]

Daniel you are lucky. Here is the direct link

http://www.ecs.umass.edu/ece/labs/vlsicad/papers/SPSim_DATE11_FINAL.pdf

and more papers can be found here
Maciej Ciesielski -- Papers

 

[Daniel Payne]

Thank you, free is always preferred to $10 or $31.

 

[kaaliakahn]

Now i need review from you and other experts on this forum regarding the merit of this paper.

Keep me posted.

Thanks