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TSMC Is No Longer Reluctant To Produce Advanced Chips In The US; Reveals Plans To Build A Cutting-Edge A16 (1.6nm) Facility In Arizona By 2030

fansink

Well-known member
Well, it seems like TSMC has chosen the US as its next place of expansion, as the firm has now revealed that it plans to produce cutting-edge chips in Arizona.

Trump's Pressure Tactic On TSMC Has Apparently Worked Out, As The Taiwan Giant Plans To Show Massive Commitment In The Region

With the Trump administration taking office, TSMC's US ambitions have grown to new levels, to a point where the firm is now determined to bring advanced chip production into the nation. According to TSMC's VP, Peter Cleveland (via Focus Taiwan), it is claimed that the company plans to produce its third fab in Arizona to sustain the "US AI leadership" and ensure that America becomes the second home for TSMC, apart from Taiwan. By these statements, the idea of a "technology transfer" certainly looks evident.

TSMC - We have not started to break ground on our third wafer fab in Phoenix. We would like to start next week. We're going to build those (high-end chips) in Phoenix to sustain the U.S.'s AI leadership.

TSMC is investing $65 billion in Arizona alone, with plans to set up a total of three facilities. The very first fab would be responsible for 4nm, and according to reports, mass production is already underway, and companies like AMD have already placed orders for their Ryzen CPUs. With the second facility, however, the Taiwan giant plans to produce higher-end chips, notably the 3nm, 2nm, and likely the A16, which is the first time we have seen mention of this particular node. The reason why this is such a significant development is that experts claim that without a "core technology" transfer, TSMC's US plans won't do much.

In a previous report, we discussed how the Taiwanese government forbade TSMC from producing 2nm offshore, citing that they won't allow Taiwan's importance in chip production to overshadow the US. However, now, with the Trump administration and how the industry's dynamics have evolved, it looks clear that TSMC won't rely "solely" on Taiwan in the future and that the company sees the US as the ideal destination for expansion, which is why some of their European projects are also said to be halted for now.

Based on what we know, TSMC's A16 (1.6nm) will likely arrive on the market by H2 2026, which means the process will be available for production in the US two years after Taiwan. While the delay is undoubtedly there, it does show that the US won't be deprived of advanced nodes and that, in the longer run, the nation could play a massive role in the semiconductor industry's dynamics.

TSMC's VP also believes that the US will account for 75% of TSMC's business in the longer run, and the Trump administration has played a key role in catalyzing this process. It seems like Trump's pressure tactics have worked out in restoring the US's chip glory, although this will take years from now on.

 
You do know that it is speculated to be ready for production in Taiwan by 2026, so its arrival in US is four years after Taiwan, not much sooner than TSMC N4 is in production in Phase 1.

If Intel keeps scheduling their Intel14A should be in production!

 
You do know that it is speculated to be ready for production in Taiwan by 2026, so its arrival in US is four years after Taiwan, not much sooner than TSMC N4 is in production in Phase 1.

If Intel keeps scheduling their Intel14A should be in production!

If intel keeps their 2yr cadence, we are talking not just 14A, but 10A HVM for over a year
 
It will be interesting to see what roadmap Intel presents next month at the foundry event. It is certainly going to be an exciting year for us.
I don't think TSMC or Intel's events this year will be too interesting. I suspect the most Intel will talk about is 1 or 2 more 18A derivatives. I'm guessing at the public opening keynote, Intel won't go into any detail about 14A or 10A. Maybe we get some new Foveros or EMIB derivatives announced? I think TSMC's events could be equally unremarkable. I think TSMC will slap A14 onto the roadmap as N2 enters HVM at the end of this year. In typical TSMC fashion, I doubt we will get substantial details beyond that. Best case is we get some high level PPA information. If memory serves, TSMC wouldn't even comment on anything about N2 other than it being GAA for like the first year after they publicly slapped it onto their roadmap. I think it was after N3 started HVM when PPA information was released. But I suppose nothing could really be worse than last year, when the only thing "new" to show was an alternative metal stack with a lower layer count stack for N4 and calling that a new node (N4C).
 
I don't think TSMC or Intel's events this year will be too interesting. I suspect the most Intel will talk about is 1 or 2 more 18A derivatives. I'm guessing at the public opening keynote, Intel won't go into any detail about 14A or 10A. Maybe we get some new Foveros or EMIB derivatives announced? I think TSMC's events could be equally unremarkable. I think TSMC will slap A14 onto the roadmap as N2 enters HVM at the end of this year. In typical TSMC fashion, I doubt we will get substantial details beyond that. Best case is we get some high level PPA information. If memory serves, TSMC wouldn't even comment on anything about N2 other than it being GAA for like the first year after they publicly slapped it onto their roadmap. I think it was after N3 started HVM when PPA information was released. But I suppose nothing could really be worse than last year, when the only thing "new" to show was an alternative metal stack with a lower layer count stack for N4 and calling that a new node (N4C).

What do you mean by “slapped”? Is that derogatory term? Have you attended these “unremarkable” events?
 
What do you mean by “slapped”? Is that derogatory term?
No, I just mean putting it on the public roadmap. For whatever reason, I frequently use slapping/slapped/slammed something down instead of placed/placing.

I don't know if this is the right way to phrase it, but I also feel like that verbage differentiates it from when various technologies enter the internal roadmap and or the NDA only roadmap which is more detailed and extends far further into the future than when a company "slaps something" onto their public roadmaps.
Have you attended these “unremarkable” events?
I am not saying that they are all unremarkable. Rather that I suspect this year Intel's and TSMC's could be because they don't want to talk about "what's next" in any particularly large amount of detail for competitive reasons. After all, TSMC has always been cagey; and Intel presumably doesn't have anything to prove now that they have shown they can go head to head with TSMC. In the words of CC Wei when people asked him about how N2 performed vs N3 when that wasn't yet public info "those who need to know know...". IMO neither of them has anything to gain by being too transparent and giving the other a clearer idea of what the other is doing.

I also think ambiguity really helps TSMC here. TSMC has been on a 3 year between nodes (6 year development cycles) vs the old 2 year gap (4 year development cycle). If that trend holds, A14 would be coming out in 2029 (when Intel says 10A would be launching products). Which just doesn't feel right. TSMC is too fearsome to just let Intel walk away with a full node lead. Now, maybe TSMC A14 is a more than 1 process node uplift/a HUGE improvement over N2/A16 and is comparable to or even better than i10A? But that feels too reminiscent of intel "hyperscaling" for me to imagine that TSMC will follow that strategy. So maybe TSMC is down to 4 or 5 year development cycles again and A14 is coming in 2028? But that theory disagrees with recent statement's from TSMC's R&D department that increasing complexity has made even 5-year cycles too aggressive and 6+ years would be the standard going forward for the time being. Obviously, TSMC and their customers know the answer (whatever it is). Either way, we are talking at least 3+ years from now, and it certainly doesn't hurt TSMC to make the lives of Intel and Samsung's competitive intelligence divisions harder.

But back on topic; I do think last year's TSMC symposium was lame from a process technology perspective. Something like N4C in any other year would not be interesting enough to be called a node nor would TSMC be talking about it on the big stage. But what are you going to do. TSMC has already talked about many specialty derivatives on multiple established process nodes, early N3 derivatives, and N2/A16. Clearly there wasn't anything else coming soon enough for TSMC to want to show it off. Maybe there was some interesting EDA stuff that tickled your fancy? I think I remember seeing some stuff about analog migration tools on N2 since there is no thick gate at last year's symposium. While kind of neat, that isn't super interesting from a process technology perspective. If anything, it is something of a failure from the wider industry that this normally standard capability is not available on GAA (at least so far). If anyone was going to do it, you would think maybe TSMC. But unfortunately, they couldn't get it working well enough to put an iron clad TSMC commitment to their customers on that. Maybe one day, one of the big three will offer thick and thin gate on GAA, but that day is unfortunately not today.

And before you say it, no, I don't think this is a reflection of TSMC's capability, and my statement isn't meant to disparage them. After all, Samsung and Intel haven't mentioned finding a good solution (nor has thick gate shown up in SF3E or SF3 teardowns). If Intel or Samsung did, I assume one of them would be bragging about it, because having thick and thin gate on the same wafer would be a very impressive accomplishment. The real problem is GAA is just absurdly hard and a lot of things that work in finFET physically don't work well in GAA land. Such as the afore mentioned space to support thick gate due to the limited spacing between nanosheets, PMOS channel mobility, and also PMOS compressive strain.
 
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. The real problem is GAA is just absurdly hard and a lot of things that work in finFET physically don't work well in GAA land. Such as the afore mentioned space to support thick gate due to the limited spacing between nanosheets, PMOS channel mobility, and also PMOS compressive strain.

The reality of you really are in the trenches even N3 and the physics, chemistry of making go > 30B transistors 50B or more Via and contacts work where the smallest systemic assumetries or funny surface artifacts make for yield, performance or reliability issues. It’s magically ….
 
No, I just mean putting it on the public roadmap. For whatever reason, I frequently use slapping/slapped/slammed something down instead of placed/placing. I don't know if this is the right way to phrase it, but I also feel like that verbage differentiates it from when various technologies enter the internal roadmap and or the NDA only roadmap which is more detailed and extends far further into the future than when a company "slaps something" onto their public roadmaps.

Have you attended a TSMC Technical Symposium in Silicon Valley? It really is something to see. Very well prepared and they know full well that anything that is presented will be click-baited in the media the next day. When the symposiums first started the press was not allowed. Even today the press are not allowed in all of the sessions. It is clearly posted that no recordings can be made and no photographs can be taken yet they always are, so what is TSMC going to do? They are going to be very careful what is said and they are going to make sure the slides cannot be used against them.

I remember one time, this was during the Intel BK era, a picture of a defect density slide TSMC presented at a symposium ended up in an Intel slide deck. It was no longer accurate of course but was still used as competitive positioning when Intel decided to be a foundry. That was it for defect density slides at the TSMC Symposiums.

Only the paranoid survive, right?
 
If TSMC’s goal is to remain the leading-edge HVM foundry in the US, this goal won’t likely be challenged by bringing their 16A (1.6nm) node to the US any earlier than 2030, and if necessary TSMC may accelerate their plans accordingly.
 
If TSMC’s goal is to remain the leading-edge HVM foundry in the US, this goal won’t likely be challenged by bringing their 16A (1.6nm) node to the US any earlier than 2030, and if necessary TSMC may accelerate their plans accordingly.

Based on my experience, customers have more to say about this than politicians. If Apple/Nvidia/AMD/Broadcom/Qualcomm, etc... wants local manufacturing they will have local manufacturing.
 
Based on my experience, customers have more to say about this than politicians. If Apple/Nvidia/AMD/Broadcom/Qualcomm, etc... wants local manufacturing they will have local manufacturing.

Looks like TSMC's Fab 2 in Arizona, which is under construction, is targeting 3nm, 2nm, and A16 processes, with production slated for 2028.

 
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