Apple to Bring 2nm Chips to iPhone 18 as TSMC’s Yields Climb Past 70%

[fansink]

TSMC’s initial supply of 2nm chipsets will go to Apple and will likely power next year’s iPhone 18 series. Last year, it was reported that the Cupertino tech giant would be TSMC’s first customer for the N2 process node, given how it is currently the chipmaker’s largest client.

Taking to X, analyst Ming-Chi Kuo has stated that this year’s iPhone will likely skip the N2 process node, sticking with 3nm for another year. Apple first brought the N3 (3nm) to 2023’s iPhone 15 Pros, which allowed it to “reinforce” its market lead. With TSMC’s yields improving, the company is expected to move to 2nm soon.

Kuo reported that TSMC’s 2nm yields hit an industry-leading 70% three months ago and have since climbed even higher. Compare that to Samsung’s ~30% and Intel’s 10% (18A) and the gap becomes widely evident. This high yield is expected to help push mass production in the second half of this year.

Apple’s devices are said to usually start mass production a few months before launch, and with TSMC’s progress on N2, next year’s A20 Bionic could adopt 2nm. Of course, this claim is purely based on analytical information and should be taken with a grain of salt.

The key highlight about 2nm is simply how efficient it is. Early reports have indicated that it would bring 25%–30% efficiency gains alone, coupled with close to a 15% performance boost. But, it would also come at a hefty cost, which is why it can be reasonable to assume that even next year, the 2nm chips may only make it to the Pro models.

Kuo reported that TSMC’s 2nm yields hit an industry-leading 70% three months ago and have since climbed even higher. Compare that to Samsung’s ~30% and Intel’s 10% (18A) and the gap becomes widely evident. This high yield is expected to help push mass production in the second half of this year.

Apple’s devices are said to usually start mass production a few months before launch, and with TSMC’s progress on N2, next year’s A20 Bionic could adopt 2nm. Of course, this claim is purely based on analytical information and should be taken with a grain of salt.

The key highlight about 2nm is simply how efficient it is. Early reports have indicated that it would bring 25%–30% efficiency gains alone, coupled with close to a 15% performance boost. But, it would also come at a hefty cost, which is why it can be reasonable to assume that even next year, the 2nm chips may only make it to the Pro models.

Apple to Bring 2nm Chips to iPhone 18 as TSMC's Yields Climb Past 70%

TSMC's initial supply of 2nm chipsets will go to Apple and will likely power next year's iPhone 18 series. Last year, it was reported that the Cupertino

appuals.com

 

[fansink]

Not quite defect density, but...

 

[fansink]

Presuming a die size of 125 mm² (1.25 cm²) and a 70% yield, the standard defect density for the iPhone 18’s A20 chip on TSMC’s 2nm process is approximately 0.285 defects/cm².

 

[siliconbruh999]

I am going to say this is not a iPhone SoC yield it must be their test vehicle yield whatever they use.
At ISSCC the yield for SRAM was 90% based on very small die we don't know how big the die is for the claimed 70% yield.

 

[fansink]

I am going to say this is not a iPhone SoC yield it must be their test vehicle yield whatever they use.
At ISSCC the yield for SRAM was 90% based on very small die we don't know how big the die is for the claimed 70% yield.

I'm going to say, what C.C. Wei has said, and what TSMC has done.

• TSMC has stated that they expect volume production (VP) of N2 within 2H25
• TSMC CEO C.C. Wei highlights N2’s progress: "N2 technology development is progressing well with device performance and yield on track or ahead of plan, and N2 is on track for volume production in 2025 with a ramp profile like N3."
• TSMC N3 ramp profile had defect density of ~0.25 at this point in time (-2.5Q from VP).

My earlier statement "...TSMC’s 2nm process is approximately 0.285 defects/cm²" seems well within what C.C. Wei has said, and what TSMC has done.

 

[siliconbruh999]

I'm going to say, what C.C. Wei has said, and what TSMC has done.

• TSMC has stated that they expect volume production (VP) of N2 within 2H25
• TSMC CEO C.C. Wei highlights N2’s progress: "N2 technology development is progressing well with device performance and yield on track or ahead of plan, and N2 is on track for volume production in 2025 with a ramp profile like N3."
• TSMC N3 ramp profile had defect density of ~0.25 at this point in time (-2.5Q from VP).

My earlier statement "...TSMC’s 2nm process is approximately 0.285 defects/cm²" seems well within what C.C. Wei has said, and what TSMC has done.

Which I doubt

 

[nghanayem]

Which I doubt
View attachment 2908

Why would it be doubtful that N2 DD is around N5 levels in a time adjusted manner? All credible indications point to N2 shaping up nicely as they squeeze out the last bits of performance so they can hit 100% of the final UPF target and getting DD and variation to the targets TSMC committed for Iphone 18 SOC HVM.

 

[fansink]

Which I doubt
View attachment 2908

At the 2023 North American Technology Symposium (June 2023) TSMC stated:

“the D0 defect density of N3E is at relative parity with N5, matching the defect rate of the older node for the same point in its respective lifecycle.”

During TSMC’s 4Q23 earnings call (Jan 18, 2024), Wei highlights N2’s progress:

“N2 technology development is progressing well with device performance and yield on track or ahead of plan, and N2 is on track for volume production in 2025 with a ramp profile like N3."

So N2 has a ramp profile like N3, and N3 has a ramp profile like N5, thus N2 has a ~similar ramp profile as N5, and according to C.C. Wei N2 is on track or ahead of plan.

Between on track or ahead of plan, lifecycle is -1.6Q (turquoise) or being late the lifecycle is -2.5Q (purple).

Whether N2 is closer to N5 or N7, on time, ahead, or late, still have D0 less than 0.30, likely (knowing TSMC), D0 is closer to 0.25.

That’s a lot of extrapolating, but that's where the fun is.

 

[delong.height]

Kuo reported that TSMC’s 2nm yields hit an industry-leading 70% three months ago and have since climbed even higher. Compare that to Samsung’s ~30% and Intel’s 10% (18A) and the gap becomes widely evident.

Samsung has a higher yield than Intel? Come on!

 

[Daniel Nenni]

Samsung has a higher yield than Intel? Come on!

Not true at all. The media has not been kind to Intel of late. I know companies who have done test chips and 18A yield is on target.

 

[fansink]

Not true at all. The media has not been kind to Intel of late. I know companies who have done test chips and 18A yield is on target.

I didn't even catch the Samsung's defect density is greater than Intel's, which is absolute nonsense.

I just wanted to get to the bottom of where TSMC is currently in their N2 lifecycle, and try to extract a reasonable range of defect density.

Since Apple is likely to use N2 for their 2026 iPhones, that timeline between the A20 wafer start to release date, helps to pin a date range to N2's lifecycle MP.

 

[Daniel Nenni]

I didn't even catch the Samsung's defect density is greater than Intel's, which is absolute nonsense.
I just wanted to get to the bottom of where TSMC is currently in their N2 lifecycle, and try to extract a reasonable range of defect density.
Since Apple is likely to use N2 for their 2026 iPhones, that timeline between the A20 wafer start to release date, helps to pin a date range to N2's lifecycle MP.

The TSMC Tech Symposium is next month so we will know more then, but from what I hear N2 yield is, in fact, better than expected and so are the design starts. Rest assured Apple will be on N2 next year. The semiconductor industry is full of big egos and they all want to be first on the node. Apple's semiconductor ego is not even measurable.

It is interesting to note that I have not seen another N3 based SoC from MediaTek or Qualcomm in a product shipping in volumes. Has anybody else? Is Apple really that good?

 

[fansink]

The TSMC Tech Symposium is next month so we will know more then, but from what I hear N2 yield is, in fact, better than expected and so are the design starts. Rest assured Apple will be on N2 next year. The semiconductor industry is full of big egos and they all want to be first on the node. Apple's semiconductor ego is not even measurable.

It is interesting to note that I have not seen another N3 based SoC from MediaTek or Qualcomm in a product shipping in volumes. Has anybody else? Is Apple really that good?

Can't Wait, Totally Psyched

 

[kevin01]

I didn't even catch the Samsung's defect density is greater than Intel's, which is absolute nonsense.

I just wanted to get to the bottom of where TSMC is currently in their N2 lifecycle, and try to extract a reasonable range of defect density.

Since Apple is likely to use N2 for their 2026 iPhones, that timeline between the A20 wafer start to release date, helps to pin a date range to N2's lifecycle MP.

CC Wei mentioned N2 ramp profile is similar to N3, but which N3? N3B (the original N3) was not doing well ad N3E, for example.

 

[siliconbruh999]

The TSMC Tech Symposium is next month so we will know more then, but from what I hear N2 yield is, in fact, better than expected and so are the design starts. Rest assured Apple will be on N2 next year. The semiconductor industry is full of big egos and they all want to be first on the node. Apple's semiconductor ego is not even measurable.

It is interesting to note that I have not seen another N3 based SoC from MediaTek or Qualcomm in a product shipping in volumes. Has anybody else? Is Apple really that good?

Snapdragon 8 Elite and Dimensity 9500 exists on N3E and devices based on these are available to purchase

 

[fansink]

CC Wei mentioned N2 ramp profile is similar to N3, but which N3? N3B (the original N3) was not doing well ad N3E, for example.

My SWAG is that on January 18, 2024, when C.C. Wei stated that N2’s ramp profile would be “like N3,” he was most likely referring to N3E, which had just started HVM in Q4 2023 and passed the steep D0 decline phase, though less likely he could have meant N3B, which was too mature by then.