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2023 Status of EUV pellicle use

Fred Chen

Moderator
From earlier in the year:

When will Samsung adopt EUV pellicles in chip production like TSMC?
  • Noh Tae Min 기자
  • 승인 2023.04.10 08:59
Korean tech giant likely fearing damages to pellicles that can halt line

Extreme ultraviolet (EUV) process adoption by chipmakers in their advanced chip-making is expanding rapidly in recent years.

In response to this increasing demand, many companies are developing pellicles for use in the EUV process. South Korean companies S&S Tech and FST have developed those with over 90% transmittance already.

However, Samsung is yet to adopt them and sources say this could be fear of the pellicles being vulnerable to damages that could halt the entire production line when it occurs.

Pellicles are commodities used to protect the photomask during the lithography process.

They are expensive but adopting them can allow chipmakers to use the even more expensive photomasks, which are around 500 million won to 1 billion won per unit, to be used longer, which ultimately results in overall cost reduction.

Samsung made equity investments in S&S Tech and FST in 2020 and 2021, respectively, for this reason. It spend 65.8 billion won for 8% shares in S&S Tech and 43 billion won for 6.9% shares in FST.

This support allowed the two companies to develop seemingly commercially viable pellicles within two years.

But sources said Samsung yet lukewarm in adopting these to its fabs. The main reason is the potential of the pellicles being damaged.

EUV process is a high-energy output process and could cause the pellicles to break.

If this occurs, the EUV machine, which costs millions of dollars, must be stopped to be cleaned, while the entire production that relies on the machine is also halted.

Samsung can only mitigate this risk by actually testing the pellicles on its EUV process.

There may be short-term losses from these tests but in the long-term, it is hard to deny that EUV will contribute to increasing the chipmaker’s overall productivity.

Taiwan’s TSMC is said to have gone through a similar experience but has now succeeded in adopting pellicles in its EUV process.

The company procures its pellicles from Japan’s Mitsui Chemicals (Fred's note: i.e. ASML). When first adopting these pellicles, they would occasionally break, causing TSMC to shut down the production line multiple times. Through these experiences, the Taiwanese chip giant accumulated a guideline to handle such situations.

The current chip downturn also offers Samsung such an opportunity; the production outputs of lines are at all-time low, making such tests more economically viable.

저작권자 © THE ELEC, Korea Electronics Industry Media 무단전재 및 재배포 금지
 
EUV machine redundancy is probably something only TSMC can exploit, as even Samsung does not have enough EUV machines to withstand a pellicle break. Still a hassle to clean up though. Changing masks is also a time-consuming operation, as the mask z-position needs to be confirmed to not shift the patterns differently.
 
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What would negate the use of a pellicle?

Actually what brought about the use of pellicle to protect the mask?
 
BTW, it says here that TSMC is using their own in-house developed pellicle: : https://www.anandtech.com/show/16732/tsmc-manufacturing-update

TSMC states that it’s been using an in-house developed pellicle for its EUV nodes since 2019 and more extensively in 2020. In comparison, ASML and Mitsui Chemicals only had recently a few months ago announced that they’re only planning to start volume sales of their own pellicle in 2Q21, essentially right now at the time of this article (ASML has reached out to us to clarify that they've been shipping pellicles to customers in volume for two years - thousands of units from their own production lines, and that the deal with Mitsui is solely transferring that volume production line externally). TSMC doesn’t state any technical details of their in-house pellicle, but if the N5 yields are to be a sign of the results, then it must be an important part of TSMC’s current success at leading edge nodes.
 
We talk about TSMC having so many EUV tools but I wonder if that matters as much as we say. For the sake of argument let us say TSMC has 100 and Samsung 30. Let’s say that of TSMC’s 100 steppers 15 are for N6, 15 for fab12, 45 are for N5, and the remaining 25 are for N3/E production.

For Samsung let’s say 10 are at Hwasong and 20 at Pyeongtaek. With let’s say 50% of utilization going to the couple of layers needed for their dram, and the other 50% for the many EUV layers on 7LPP and below. Since it seems like there are more SF4E and SF5 SOCs, I wouldn’t be surprised if a good chunk of the 7LPP tool time is now used for the newer versions. We also know that for DRAM as the yield and cost curves progress old lines will get converted to the new lower cost per bit process.

I say all that to say this. Because TSMC keeps old fabs running for decades, their old EUV tool shipments don’t impact or improve their capacity on new nodes. Put another way when TSMC goes to fill up the fabs they are building for N2 family they are starting from 0 steppers. Meanwhile Samsung gets to start with a slight headstart as long as it is not building a new fab. All they need is more steppers for any extra EUV layers they add as well as making up the difference for the little bit of legacy capacity they leave behind for trailing edge idm or foundry products. The one angle I could see where TSMC does have an impactful lead in EUV is HVM expertise and process integration. However as the technology keeps maturing and as other semi firms have developed multiple EUV nodes, I don’t know if this advantage is really significant anymore as we head into 2024.
 
We talk about TSMC having so many EUV tools but I wonder if that matters as much as we say. For the sake of argument let us say TSMC has 100 and Samsung 30. Let’s say that of TSMC’s 100 steppers 15 are for N6, 15 for fab12, 45 are for N5, and the remaining 25 are for N3/E production.

For Samsung let’s say 10 are at Hwasong and 20 at Pyeongtaek. With let’s say 50% of utilization going to the couple of layers needed for their dram, and the other 50% for the many EUV layers on 7LPP and below. Since it seems like there are more SF4E and SF5 SOCs, I wouldn’t be surprised if a good chunk of the 7LPP tool time is now used for the newer versions. We also know that for DRAM as the yield and cost curves progress old lines will get converted to the new lower cost per bit process.

I say all that to say this. Because TSMC keeps old fabs running for decades, their old EUV tool shipments don’t impact or improve their capacity on new nodes. Put another way when TSMC goes to fill up the fabs they are building for N2 family they are starting from 0 steppers. Meanwhile Samsung gets to start with a slight headstart as long as it is not building a new fab. All they need is more steppers for any extra EUV layers they add as well as making up the difference for the little bit of legacy capacity they leave behind for trailing edge idm or foundry products. The one angle I could see where TSMC does have an impactful lead in EUV is HVM expertise and process integration. However as the technology keeps maturing and as other semi firms have developed multiple EUV nodes, I don’t know if this advantage is really significant anymore as we head into 2024.
Well, that really depends if Samsung uses the same machines for DRAM and foundry. DRAM use can sap their capacity.
 
We talk about TSMC having so many EUV tools but I wonder if that matters as much as we say. For the sake of argument let us say TSMC has 100 and Samsung 30. Let’s say that of TSMC’s 100 steppers 15 are for N6, 15 for fab12, 45 are for N5, and the remaining 25 are for N3/E production.
As N3 / N2 have nearly double the amount EUV layers as N5, there will be a much bigger demand for EUV steppers (maybe double the demand?). Supply of EUV machines could be a limiting factor of how quickly TSMC/Samsung build more capacity, because ASML can only manufacture 50 - 60 a year.
 
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