Samsung to increase next-generation DRAM 'chip size'... HBM Yield Improvement Priority
Weigh in on yield stabilization instead of productivity... Earnings expected by the end of the second quarter
Semiconductor Display Input:2025/02/10 17:05 Modified: 2025/02/11 10:09
Jang Kyung-yoon
It is understood that Samsung Electronics has been redesigning its cutting-edge DRAM since the second half of last year in the direction of increasing the chip size. It is a strategy that emphasizes 'yield' rather than productivity and performance, and it is interpreted as a strategy to focus on stable mass production of high-value memory such as HBM (high-bandwidth memory).
According to an industry report on the 10th, Samsung Electronics has been developing 1C (6th generation 10nm) DRAM since the second half of last year by increasing the chip size compared to the existing one.
The 1C DRAM is the next-generation DRAM that Samsung Electronics aims to mass-produce in the second half of this year. The circuit linewidth is at the level of 11~12 nanometers (nm). The previous generation, 1b (5th generation) DRAM, is estimated to be in the 12~13nm range.
Samsung Electronics plans to prioritize the application of 1c DRAM to the next-generation HBM4 (6th generation HBM). The intention is to quickly increase HBM's competitiveness with DRAM, which is a generation ahead of its major competitors. SK hynix and Micron have decided to adopt 1b DRAM in HBM4.
However, Samsung's 1C DRAM has had difficulties in improving yield since the beginning of development. Although the first quantity was secured in the second half of last year, it is known that the yield was not implemented to a satisfactory level.
The main background is productivity. Initially, Samsung Electronics decided to reduce the chip size of 1C DRAM compared to the original plan in consideration of competitors. The smaller the chip size, the higher the output compared to the wafer input, which is advantageous for manufacturing cost efficiency. However, it has been pointed out that this reduces stability.
As a result, Samsung Electronics decided to make some changes to the design of 1C DRAM at the end of last year. The main goal is to keep the linewidth of the core circuit to a minimum, but to relax the linewidth standard of the surrounding circuits to increase the yield quickly.
A source familiar with the matter explained, "Samsung Electronics has changed its design to increase the chip size of 1C DRAM and is working hard to improve yield by the middle of this year," adding, "It seems that Samsung Electronics is focusing on stable mass production of next-generation memory even if it costs more."
It is still too early to discuss the significant yield of 1C DRAM with a changed design. Inside and outside Samsung Electronics, it is expected that concrete results will be drawn by May~June.
On the other hand, for similar reasons, some products of 1b DRAM are also being redesigned to improve yield. Currently, it is reported that work is underway to raise the yield rate of 32Gb (Gigabit) 1b DRAM products for servers to the mass production level of 70~80%.
Reporter Jang Kyung-yoon jkyoon@zdnet.co.kr
https://zdnet.co.kr/view/?no=20250210164808#_DYAD (Auto translated)
Weigh in on yield stabilization instead of productivity... Earnings expected by the end of the second quarter
Semiconductor Display Input:2025/02/10 17:05 Modified: 2025/02/11 10:09
Jang Kyung-yoon
It is understood that Samsung Electronics has been redesigning its cutting-edge DRAM since the second half of last year in the direction of increasing the chip size. It is a strategy that emphasizes 'yield' rather than productivity and performance, and it is interpreted as a strategy to focus on stable mass production of high-value memory such as HBM (high-bandwidth memory).
According to an industry report on the 10th, Samsung Electronics has been developing 1C (6th generation 10nm) DRAM since the second half of last year by increasing the chip size compared to the existing one.
The 1C DRAM is the next-generation DRAM that Samsung Electronics aims to mass-produce in the second half of this year. The circuit linewidth is at the level of 11~12 nanometers (nm). The previous generation, 1b (5th generation) DRAM, is estimated to be in the 12~13nm range.
Samsung Electronics plans to prioritize the application of 1c DRAM to the next-generation HBM4 (6th generation HBM). The intention is to quickly increase HBM's competitiveness with DRAM, which is a generation ahead of its major competitors. SK hynix and Micron have decided to adopt 1b DRAM in HBM4.
However, Samsung's 1C DRAM has had difficulties in improving yield since the beginning of development. Although the first quantity was secured in the second half of last year, it is known that the yield was not implemented to a satisfactory level.
The main background is productivity. Initially, Samsung Electronics decided to reduce the chip size of 1C DRAM compared to the original plan in consideration of competitors. The smaller the chip size, the higher the output compared to the wafer input, which is advantageous for manufacturing cost efficiency. However, it has been pointed out that this reduces stability.
As a result, Samsung Electronics decided to make some changes to the design of 1C DRAM at the end of last year. The main goal is to keep the linewidth of the core circuit to a minimum, but to relax the linewidth standard of the surrounding circuits to increase the yield quickly.
A source familiar with the matter explained, "Samsung Electronics has changed its design to increase the chip size of 1C DRAM and is working hard to improve yield by the middle of this year," adding, "It seems that Samsung Electronics is focusing on stable mass production of next-generation memory even if it costs more."
It is still too early to discuss the significant yield of 1C DRAM with a changed design. Inside and outside Samsung Electronics, it is expected that concrete results will be drawn by May~June.
On the other hand, for similar reasons, some products of 1b DRAM are also being redesigned to improve yield. Currently, it is reported that work is underway to raise the yield rate of 32Gb (Gigabit) 1b DRAM products for servers to the mass production level of 70~80%.
Reporter Jang Kyung-yoon jkyoon@zdnet.co.kr
https://zdnet.co.kr/view/?no=20250210164808#_DYAD (Auto translated)