1) Given Input clock design frequency = 200hz Write RTL code in Verilog to genera

[dehuniyad]

1) Given Input clock design frequency = 200hz

Write RTL code in Verilog to generate one minute and one second pulses based on the input clock frequency . Reset is asynchronous reset ,active
low .




module clock(input clock,reset,
output reg min_p,sec_p);
reg [7:0]count;
reg [5:0]sec;

always @(posedge clock or negedge reset)
begin

if(~reset)
begin
min_p <= 0;
sec_p <= 0;
count <= 0;

sec <= 0;
end
else

begin

count <= count +1;
min_p <=0;
sec_p <=0;
if(count == 8'd199)
begin
count <= 0;
sec_p <= ~sec_p ;
sec <= sec +1;
if(sec == 6'd59)
begin
sec <= 0;
min_p <= ~min_p;
end
end
end
end
endmodule