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Search results

  1. S

    The Intel Split

    TSMC makes more wafers than Intel but at the leading edge their volumes are a lot closer than you think. Intel has enough volume, they just need to execute a lot better.
  2. S

    The Intel Split

    I don't understand this, Intel buys all their tools just like everyone else, they don't make their own tools.
  3. S

    Airlines warn of 'catastrophic' crisis when new 5G service is deployed

    Many years ago I ran a wafer fab and we had multiple incidents of a cell phone ringing near a piece of equipment and the equipment going into pump down. It was only certain phones and our group used Nextel phones for internal communications and never had an issue. We made all visitors turn off...
  4. S

    Airlines warn of 'catastrophic' crisis when new 5G service is deployed

    I don't understand this, I have a 5G hot spot and use it with a 5G connection all the time, I have three 5G capable phones as well. 5G has been "turned on" for a long time.
  5. S

    EUV's productivity, and 157i

    I think your take on EUV is way too pessimistic. - EUV is in high volume production for 7nm and 5nm and ramping for 3nm. - ASML continues to introduce system improvements with each new system offering higher throughput, higher uptime and better precision. - 3400B was the primary system for 7nm...
  6. S

    Wafer size / fab processing questions

    "Thank you, the terminology + summary helps me understand." Beam tools is a classification that came out of the 450mm work, if you can find some of the old articles they talk about it. "Is there a simple reason for that? (and is this something that I can find out myself reading something on...
  7. S

    Wafer size / fab processing questions

    There are basically two classes of tools, beam tools and non-beam tools. Beam tools scan the wafer; exposure, implant and some inspection and metrology tools are beam tools. All other fab tools are non-beam tools. For beam tools throughput is more complex than you are considering because there...
  8. S

    GAA Is Ready for Customers’ Adoption – 3nm MP in 2022, 2nm in 2025

    I estimate 180MTx/mm2 for Samsung 3 and 185MTx/mm2 for TSMC 5, so Samsung 3 is slightly less dense than TSMC 5.
  9. S

    Do wafer costs vary significantly based on product type?

    They are dramatically different. IGBT processes are much simpler and there is no such thing as a 28nm IGBT any way. IGBTs are typically 600 volts plus and there is no reason to use such small line widths. If you really want to know what IGBTs cost you can buy our Discrete and Power Products Cost...
  10. S

    Low yields driving calls for EUV pellicles

    You took a post from another web site, copied it and posted it here. The post implies that pellicles aren't available or aren't being used, I simply pointed out that pellicles are available and are being used on some layers. Now you are trying to change the conversation by saying they are still...
  11. S

    Low yields driving calls for EUV pellicles

    Pellicles are available now and in fact are being used on some layers in production today. ASML is also introducing a new higher transmission pellicle. This is old news.
  12. S

    CES 2021 Intel new cpu. Question about the 10nm yield

    I think the yield issue is how they are patterning M0 and M1, the whole sequence is unlike anything I have ever seen. I recently saw SEM images of the 10nm Super Fin M0 and M1 layers from TechInsights and the patterns look terrible.
  13. S

    Intel to Focus on Truth and Transparency!

    For TSMC going from 7nm to 5nm they have taken multi-patterned layers and converted them to EUV. Multi-patterned layers have multiple masks with complex mask interactions requiring complex design rules. EUV is much more straight forward from a patterning and design rule perspective. For Intel...
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