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Analyzing their reported financials I can tell when they start reporting the depreciation and they start reporting it around when they start reporting revenue. You can express all the opinions you want but that is what the numbers say they actually do for their production equipment.
I think it is the opposite, you don’t want to have depreciation expenses hitting your P&L dragging down profitability until you have offsetting revenue.
Intel D1 is really complex, there is mod 1, mod 2, and mod 3, different nodes in different phases of development/production in each. R&D costs and depreciation likely all hit the R&D line but when a mod starts running initial production then it would start being charged to cost of goods sold.
I can tell you for a fact that through Q1 of 2024 none of the 5nm equipment is fully depreciated. My costs match their financials within about 2% and I have everything still depreciating. When Q2 comes out I will check again.
I can tell when equipment starts to become fully depreciated from TSMC's financials and some analysis techniques I have. when they report their quarterly results I get a very strong signal if anything drops off for depreciation. Sometimes after the fact I find out they started depreciation a...
Another comment on this is there are tax rules and then what companies use for reporting, those are often not the same and they may keep two sets of books. So while Taiwan allows 3 year depreciation for taxes, TSMC uses 5 years for reporting and their public financial statements are based on this.
Depreciation starts on equipment when it enters production and then TSMC depreciates equipment for five years per their annual report.
The other thing is that TSMC brought up Fab 18 phase 1 and then ramped it up over time, and then phase 2 and ramp and then phase 3 and ramp. If you put 10k wpm...
TSMC uses five year depreciation for equipment as disclosed in their annual report. Depreciation doesn't start until equipment is in production, I am not confusing anything, 100% of TSMC's 5nm equipment is still depreciating!
The other thing to keep in mind is they started phase 1 and then...
None of the "N5 Fab 18a" equipment is depreciated yet, your "mostly depreciated" statement is wrong.
When equipment is still depreciating that makes it even more important to keep the fab full. Any price above variable cost helps absorb fixed cost so you drop prices to at least absorb some of...
Historically when utilization goes down the foundries drop prices to fill the fabs, and when utilization goes up prices go up. Since the Pandemic TSMC's attitudes seems to be raise prices every year no matter what. The 3nm ramp is spoken for but they have unused capacity at all nodes 5nm and...
What gap? I have done a ton of modeling of Intel over the years and confirmed/correlated results to published and private numbers. If a fab has a capacity of 100K wpm and is running 50K that is called utilization and it varies for all fabs, it is fully factored into my modeling. And while Intel...
He said Intel has ~200k wpm starts, if that is correct their Fab utilization isn't good because they have a lot more capacity than that and they are adding more all the time.
With respect to wafer cost the only yield that matters at all is line yield in the fab and everyone is in the high ninety percentiles. If you talk about die cost then die yield comes in and that is where Intel struggled at 14nm, and 10nm. Reportedly i4/i3 die yields are pretty good.
I have actual numbers for 18A pitches, I can't publish them but I can say that 18A high density cell transistors per mm2 are slightly higher than TSMC 5nm but lower than TSMC 3nm. To even catch up to TSMC 2nm, Intel 14A would need a big density jump and this is during a time when density jumps...
When comparing wafer costs there are two components, one is process cost and the other is fab cost. Intel 10/7 processes are very expensive processes compared to TSMC 7nm even if run in the same fab. Intel fabs are generally in higher cost countries plus Intel has some Intel specific cost...
This is an interesting slide:
- Performance/watt - I agree with their ratings.
- Density - I don't agree with, TSMC is way ahead of 18A, maybe Intel could catch up at 14A but it would take a huge jump.
- Wafer cost - surprisingly, I was just looking at wafer cost and through 18A I think they are...
"The cost of 2nm chips is very high. Research institutions pointed out that compared with 3nm, the cost will increase by 50%, and the single cost of each wafer will climb to US$30,000; therefore, the first batch of adopters will still be smartphone chips. Customer—Apple."
When 3nm was still in...
"As many on this forum are aware, maximum theoretical logic density is often calculated by taking the (M2 pitch) X (M2 tracks for a four transistor NAND gate) X (CPP). From there we try to use correction factors to account any boundary scaling (for example Scotten using 10% area reduction from...
