Thanks, all, for the discussion! I'm an author on the report. Initially, I'd note that we don’t expect our calculations to produce precise predictions of TSMC wafer prices at each node. Instead, our goal was to produce as good of a methodology as we could based on open-source data -- with the hope that more people can build on this technique so we can all better understand the nuts and bolts of the economics of the industry. At the end of the day, we were interested in what the broader economics might dictate, without trying to make assumptions to “fix” the numbers in any particular direction if we thought they were too low or too high. Certainly, I'd expect the actual numbers to be different -- and if someone has insider info from TSMC or fabless companies working with TSMC, I'd obviously trust them more! And I’d be eager to see them if someone is allowed to publish them.
Response to hist78
: I wish I’d labeled the table more clearly, but the surrounding text defines “chip” for the purposes of the table to include the same number of transistors at each node (with a baseline of the 5 nm chip having a ~600 mm^2 die). This is why the 5 nm “chip” is still cheap.
Response to BobbiMac
: The per “chip” costs do take into account die size (as I mentioned above) and yield (also discussed in the text).
Response to Fred Chen
: You get 76% if you divide 12753 by 16724 (which is capital investment per wafer processed per year in line 2) rather than by 16988 (which is the foundry sale price per wafer in line 7). If you divide by the latter, you get 75.07%.
Response to Tanj
: Re your comment depreciation: we took TSMC's reported depreciation rates, and applied them linearly going back about four years (as equipment typically depreciates according to a 4-5 year schedule). Of course, there are complications because we are using company-wide and equipment-wide depreciation numbers, and the specifics could vary quite a bit for the specific tools TSMC is using for each node. We could of course have put in different depreciation by hand based on what we think the prices should be, but that would have assumed the conclusion, and we wanted to develop a method that was independently justifiable. That said, I'd be curious about what people think is a better way to depreciate.
Re your comment on “other costs and markup” in line 6: We explained in the paragraph preceding the table that we just used TSMC's ratio of capital consumed to other costs and markup and used that same value across all nodes. We then reference endnote 216 which heavily qualifies the justification for the flat ratio -- it’s a non-ideal assumption, but these costs are somewhat of a black box, as TSMC doesn’t report these other costs and markup per node. We played around with different models with different ratios across different nodes, but unfortunately, were not able to do so in a principled way (at least with open-source data), and therefore stuck with the flat ratio. I would be curious if others have thoughts on how exactly TSMC allocates these other costs and markup across nodes.
That said, it’s quite plausible for many costs to be higher at leading-edge nodes than older ones: R&D is largely spent at the leading-edge, labor costs could be higher until processes mature, and TSMC can presumably charge greater markup for 5 nm. That said, if Daniel Nenni
is right that 5 nm is an overestimate but 16 and 10 nm are underestimates, then I would guess that the line 6 estimates are where one could add modifications to get more accurate numbers. It’s also possible TSMC might decide to sell at particular prices that are different than what the observable economics might suggest.
Finally, IC Insights does similar calculations
-- our results line up with theirs up to 28 nm, but sadly, they haven't published (anywhere I can find) results for individual leading-edge nodes (besides grouping everything 20 nm and below). I’d be curious what their latest estimates look like.