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5nm wafer cost very high

Fred Chen

Moderator
The cost of a 5nm wafer was recently reported:

.

The wafer cost had progressively increased from 16 to 7 nm at ~50% per node, but totally blew up at 5nm (nearly double that at 7nm). The use of EUV is an obvious culprit. Mask count at 7nm was slightly higher than for 5 nm, from TSMC's IEDM 2019 paper.
 

Daniel Nenni

Admin
Staff member
The cost of a 5nm wafer was recently reported:

.

The wafer cost had progressively increased from 16 to 7 nm at ~50% per node, but totally blew up at 5nm (nearly double that at 7nm). The use of EUV is an obvious culprit. Mask count at 7nm was slightly higher than for 5 nm, from TSMC's IEDM 2019 paper.
Fred, those number are not correct. The 5nm numbers are too high. FAKE NEWS:

Foundry Fake Wafer Pricing.jpg
 

hist78

Member
Fred, those number are not correct. The 5nm numbers are too high. FAKE NEWS:

View attachment 251
Wandering if the 5nm per wafer price is too high, what would you think a more reasonable price range should be?

Another thought is that even if 5nm number is too high, according to the analysis the average 5nm per chip cost is only $5 more than the 7nm's. Considering 5nm's improvement in density, performance, and energy consumption, it's really a very attractive value proposition.
 

Tanj

Member
There are two anomalies in that table. One is that depreciation is 4 years straight line, but has been recalculated for another 4 years for 7nm after subtracting 50% for the first two years. But, one can argue about that. Re-base it, or drop it to zero cost in 2 years? Either way it is simply an accounting artefact. There is plenty of use for the 7nm line for years, and the depreciation curve arguably should be redone to match the utility / rate they can charge customers.

The much bigger shift and one needing explanation is the huge jump in other costs. Presumably a large part of that is mask costs? What else would explain $5k jump relative to 7nm? And only the EUV part of the process is changed, all the DUV consumables and masks should remain about the same or actually drop due to reduction in steps.
 

Fred Chen

Moderator
In Table 9, Line 6 looks like 76% of Line 4, which is Line 2 minus depreciation. However, this was not explained that way by the authors. I have asked CSET for the clarification.
 

Fred Chen

Moderator
In Table 9, Line 6 looks like 76% of Line 4, which is Line 2 minus depreciation. However, this was not explained that way by the authors. I have asked CSET for the clarification.
The author replied; basically the 76% is a consequence of an alternative expression of their formula, where Line 6/Line 7 is their stated 75.07%. He also will join the forum for further interaction. Looking forward to it!
 
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saifmk

New member
Thanks, all, for the discussion! I'm an author on the report. Initially, I'd note that we don’t expect our calculations to produce precise predictions of TSMC wafer prices at each node. Instead, our goal was to produce as good of a methodology as we could based on open-source data -- with the hope that more people can build on this technique so we can all better understand the nuts and bolts of the economics of the industry. At the end of the day, we were interested in what the broader economics might dictate, without trying to make assumptions to “fix” the numbers in any particular direction if we thought they were too low or too high. Certainly, I'd expect the actual numbers to be different -- and if someone has insider info from TSMC or fabless companies working with TSMC, I'd obviously trust them more! And I’d be eager to see them if someone is allowed to publish them.

Response to hist78: I wish I’d labeled the table more clearly, but the surrounding text defines “chip” for the purposes of the table to include the same number of transistors at each node (with a baseline of the 5 nm chip having a ~600 mm^2 die). This is why the 5 nm “chip” is still cheap.

Response to BobbiMac: The per “chip” costs do take into account die size (as I mentioned above) and yield (also discussed in the text).

Response to Fred Chen: You get 76% if you divide 12753 by 16724 (which is capital investment per wafer processed per year in line 2) rather than by 16988 (which is the foundry sale price per wafer in line 7). If you divide by the latter, you get 75.07%.

Response to Tanj: Re your comment depreciation: we took TSMC's reported depreciation rates, and applied them linearly going back about four years (as equipment typically depreciates according to a 4-5 year schedule). Of course, there are complications because we are using company-wide and equipment-wide depreciation numbers, and the specifics could vary quite a bit for the specific tools TSMC is using for each node. We could of course have put in different depreciation by hand based on what we think the prices should be, but that would have assumed the conclusion, and we wanted to develop a method that was independently justifiable. That said, I'd be curious about what people think is a better way to depreciate.

Re your comment on “other costs and markup” in line 6: We explained in the paragraph preceding the table that we just used TSMC's ratio of capital consumed to other costs and markup and used that same value across all nodes. We then reference endnote 216 which heavily qualifies the justification for the flat ratio -- it’s a non-ideal assumption, but these costs are somewhat of a black box, as TSMC doesn’t report these other costs and markup per node. We played around with different models with different ratios across different nodes, but unfortunately, were not able to do so in a principled way (at least with open-source data), and therefore stuck with the flat ratio. I would be curious if others have thoughts on how exactly TSMC allocates these other costs and markup across nodes.

That said, it’s quite plausible for many costs to be higher at leading-edge nodes than older ones: R&D is largely spent at the leading-edge, labor costs could be higher until processes mature, and TSMC can presumably charge greater markup for 5 nm. That said, if Daniel Nenni is right that 5 nm is an overestimate but 16 and 10 nm are underestimates, then I would guess that the line 6 estimates are where one could add modifications to get more accurate numbers. It’s also possible TSMC might decide to sell at particular prices that are different than what the observable economics might suggest.

Finally, IC Insights does similar calculations -- our results line up with theirs up to 28 nm, but sadly, they haven't published (anywhere I can find) results for individual leading-edge nodes (besides grouping everything 20 nm and below). I’d be curious what their latest estimates look like.
 

saifmk

New member
Great point that the same fabs are used for some of these nodes. We didn't take this explicitly into account, and I agree that it would improve the analysis. (I'd also note that we were especially interested in the overall trendline of costs, and accepted some degree of node-to-node error.) That said, I'm not sure how much of a difference that adjustment would make. First, the existing fabs wouldn't come "free" -- that cost still needs to be taken into account. Second, according to SEMI, tools are 80% of fab costs, and I suspect that moving from 20 to 16nm or 10 to 7nm required some tool upgrades, especially given the major process changes (e.g. in the case of 20 to 16, moving from planar to FinFET). Third, the same logic from my comment earlier about "other costs and markup" would apply -- there will be additional R&D, etc. All of that said, happy to be corrected if you think any of the above is wrong!
 

Daniel Nenni

Admin
Staff member
I'm confident the above is wrong, especially the gaps between 10nm - 7nm and 7nm - 5nm. I'm just trying to figure out why. And I do appreciate your direct responses so I don't have to make assumptions from your report. By the way, I suspect that the fab/equipment for 10nm and 7nm is in fact identical.

Two more questions:

How do you account for EUV in 5nm? Is that the reason for the large price increase?

Is yield important to your methodology? Can you explain your yield calculation in more detail?




Great point that the same fabs are used for some of these nodes. We didn't take this explicitly into account, and I agree that it would improve the analysis. (I'd also note that we were especially interested in the overall trendline of costs, and accepted some degree of node-to-node error.) That said, I'm not sure how much of a difference that adjustment would make. First, the existing fabs wouldn't come "free" -- that cost still needs to be taken into account. Second, according to SEMI, tools are 80% of fab costs, and I suspect that moving from 20 to 16nm or 10 to 7nm required some tool upgrades, especially given the major process changes (e.g. in the case of 20 to 16, moving from planar to FinFET). Third, the same logic from my comment earlier about "other costs and markup" would apply -- there will be additional R&D, etc. All of that said, happy to be corrected if you think any of the above is wrong!
 

saifmk

New member
You might be right that a lot of fab equipment is identical for 10 nm and 7 nm. Still, I think there are at least some cases where new tools are needed. For example, TSMC started using EUV for some layers of its more advanced 7 nm process; and depending on which generation of ASML's EUV tools they used, they might have needed to buy a new generation of DUV tools. (See more details here.)

EUV costs would be baked into the "capital investment per wafer processed" estimates in line 2. Those numbers represent the point on the trendline across a scatterplot of TSMC's capital investments in its GigaFabs. For each node, we used the point on the trendline corresponding to when TSMC was in the early stages of mass-producing that node. Since TSMC's capital investments in 2020 include lots of EUV tools, they would be captured.

I think a bit part of the price increases for leading-edge nodes (including for 5 nm) are due to (1) depreciation schedules we used, combined with (2) the flat ratio of capital costs to other costs and markup, as I explained in a previous comment. The calculations for leading-edge nodes (before full depreciation has kicked in) are sensitive to the amount of depreciation; and although I think the broad contours how we applied TSMC's depreciation is reasonable, it would also be quite reasonable to make some modifications to the depreciation schedule to get different results. Due to the way we made the calculations, this would also have a knock-on effect to other costs. Additionally, 5 nm is the only one with no depreciation applied, but given how quickly tools depreciate, the model would reduce the 5 nm wafer price over time.

Yield came into play in the model only when calculating the per "chip" costs. Therefore, for our purposes, assume that the wafer prices simply represent wafers with whatever yield a given node is capable of producing.
 

Daniel Nenni

Admin
Staff member
I'm looking at your methodology which is why I asked about yield. I have the same question about 5nm design costs. How does that factor in?

Did you notice that the DUV/EUV article references GF 7nm and not TSMC 7nm? Kind of ironic.

"Each node corresponds to the transistor size (expressed in terms of length)" You need to fix that.

Let me give this more thought and talk to some friendly chip companies. I am really curious as to why your numbers are off. Maybe I can help you get closer to the truth.
 

saifmk

New member
I did notice it references GF 7 nm, but was citing it to refer to EUV/DUV compatibility requirements. TSMC's N7+ also uses EUV for some layers and DUV for others (see here).

Foundry price doesn't include design costs. Design costs are accounted for separately (see p. 24 and 41).

And yes, that line you noted is not wonderfully worded. Even though it's a long article, we were keeping the main text less technical, so didn't talk talk about e.g. gate length or what nodes really mean in the main text. Oh well. I might have worded it a bit differently though. :)

I'd love to hear from the chip companies!
 

Daniel Nenni

Admin
Staff member
The design cost numbers you referenced for 5nm are on the very high side as well. That's the problem with getting numbers off the internet versus the companies that actually design.

TSMC introduced EUV at 7+ with limited layers. 6nm increased EUV layers and optimized the PDK (same fab as 7nm). 5nm has what we would call full EUV. EUV is expensive in regards to equipment but it reduces the number of masks used which is a significant cost savings. Is that accounted for in your methodology? Or just the CAPEX? EUV also simplifies design which is another cost savings.

TSMC 3nm PDKs are out. Since 3nm is an optimized version of 5nm (same fabs) it should plug right into your methodology?

Are you familiar with Scott Jones and IC Knowledge? I find Scott's cost numbers to be the most accurate, in fact his models are used throughout the industry and viewed as the gold standard. Scott has 3nm models I suspect.
 

saifmk

New member
Design costs: I used data from IBS (and Gartner which matches up with similar estimates); IBS in particular has been cited by lots of industry folk (including I think SIA) and industry analysts, so I assumed it is at least reasonable. That said, they provide generic costs independent of die size or type of chip -- I'd be keen to see more granular analysis.

We used capex, and do not account for all the specific process changes e.g. different numbers of masks. (As mentioned, our focus was on the bigger-scale trends, which I think capex captures.) I'd love to try a more process-specific analysis, but it's a big task. I'd also be keen to see others try. Also, thanks for the comments on TSMC's process evolution -- my only point was to suggest that there *do* appear to be some tool upgrades from 10 to 7 nm, though let me know if I'm wrong! :) In theory, yes, 3 nm could be plugged in.

I've seen some of Scott's work, but maybe not the specific models you're talking about. If you have any useful links, please do share!
 
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Fred Chen

Moderator
The mask count from 10nm to 5nm was comparable according to TSMC (at IEDM 2019). The main point they made was they had expected many more masks at 5nm without EUV.
TSMC mask count from 16 to 5.png

That said, they do have special EUV mask handling in the fab (cleaning) due to lack of pellicles.
 

Daniel Nenni

Admin
Staff member
Scott links:



Scott is AFK this week. I will speak with him when he returns.
 
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