That amount of EUV High NA i.e. 6 is really underestimate, because SK Hynix will have this much in Q4 2028.
Whether the machine is mature enough for production vs whether the machine is mature enough to place an order is not the same concept. The only thing that might not be mature enough is the strength of the light source, and that part is always upgradable.
There isn't any High NA Machine installed, I used Google AI, all article mentioned "Will Be" but not Installed, there isn't any High NA EUV machine owned by TSMC, the one that TSMC can access is the one that is with an EU research (government owned - IMEC I think), not fully owned by TSMC. This is so minor, because even then you don't have 10 machine, it didn't make the mix, 1/2/3 machine is not important, the point is that no HVM of High NA EUV ~2035.
A funny way to interpreted this from CC Wei "他更幽默地補充,公司不僅沒有不投資,實際上「已經買了,而且買幾台就不好意思講」" Yes We brough it, it was 0.5 machine, I shared that with IMEC
No way that it will be in 2029, timeline just don't cut it. 2026 N2, 2027 N2P, 2028 N2U/A16 2029 A14 that is a more realistic situation.
Doing a node is not like playing with sand, even they mentioned full backward compatibility (EDA), when things change, there is a lot of things needed to be reverify, design backward compatibility is not equal to supply chain backward compatibility, i.e. things still needed to reverify, to be fair, it take 2-5 years to design and/or upgrade the design of a Chip. It is not like because of TSMC schedule, please push this from A16 to A14 or push that from N2 to N2P. That is not how it works.
To be backward compatibility meant that the design is more towards the 2 years rather than 5 years, not like will enable switching from node to node.
Planning this out, AMD is off, the Zen 6 is already on N2P, can't see Zen 6+ only see Zen 7 should be in 2030, nVidia is out since the size of the chip to do A16 on as launch customer is just asking for trouble, so Meditek, Apple, Google Mobile left.
I am not the one who can say anything, but in my point of view, A10 or 10A needed to be CFET, Intel VSLI recent is gearing towards that. Because 18A is a 4 stack GAA and N2 is a 3 stack GAA, just make 18A easier to achieve CFET (since it is higher to start of with).
If you don't agree that TSMC will only have the High NA EUV with meaning production volume only in 2035 then show me the place where CC Wei that he purchased and where it will be Installed, even with Taiwanese efficiency, High NA machine is substantive larger, which building currently being build to house that 10 machine, where is the plan = "0", if you plan now, building 3-5 years, 2 years to install the machine i.e. 10 machines, that will give you HVM 2035 timeline, ASML is not going to pre assemble the High NA machine, the part will not be store in ASML locations, it will be at the customer site, sorry, if you still have 3-5 years before you get the correct site, then talk to me 3 - 5 years time. Get your construction permit and plan and everything ready.
In my opinion, I am not underestimate TSMC and overestimate Intel, I am actually overstated TSMC and understated Intel. That is my point of view, TSMC in my point of view is only worth 1/4 of todays market cap