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Surely the biggest issue with TSMC adopting high-NA is not just the economics/throughput, but the sheer number of machines that would be needed to support the massive market demand (with several GigaFabs for each new node) compared to the rate that ASML can make them -- and especially, the rate that Zeiss can make the optics?
It's a lot easier for a smaller-volume foundry like Intel, they only need a fraction of the number of high-NA tools that TSMC would...
Surely the biggest issue with TSMC adopting high-NA is not just the economics/throughput, but the sheer number of machines that would be needed to support the massive market demand (with several GigaFabs for each new node) compared to the rate that ASML can make them -- and especially, the rate that Zeiss can make the optics?
It's a lot easier for a smaller-volume foundry like Intel, they only need a fraction of the number of high-NA tools that TSMC would...
Intel will probably need fewer units, but the challenges of cost and throughput may not be any less—if not greater. For example, ideally, the more High NA EUV tools that are installed and the more chips that are produced, the less of the expensive initial R&D cost each chip must bear. Economies of scale are critical in leading-edge semiconductor manufacturing.
Another problem is that if you don't have enough machines and sufficient throughput/output, large-volume customers simply can't afford to use your services. As a result, you limit yourself to becoming a niche manufacturer for small orders. That's not necessarily bad, but the margin for error or delay is slim.
