Webinar: What it really takes to build a future-proof AI architecture?

Online

Abstract As AI workloads increasingly dominate numerous cloud and edge applications, building a scalable, efficient, and future-ready AI chips is no longer optional—it's essential. This webinar explores the latest AI trends, highlighting the growing demand for intelligent processing closer to the data source and the critical role of NPUs in enabling this shift. We’ll dive …

Webinar: Unpacking System Performance: Supercharge Your Systems with Lossless Compression IPs

Online

*WORK EMAIL IS REQUIRED* As data volumes surge across cloud, AI, automotive, and edge systems, efficient lossless compression has become essential for meeting performance, latency, and bandwidth constraints. This webinar explores the trade-offs and strengths of the industry’s leading compression algorithms—GZIP, LZ4, Snappy, and Zstd—highlighting how hardware-accelerated implementations can overcome the limitations of software-based solutions …

Vivado Quick Start with Versal Devices Workshop

Online

This online workshop introduces key concepts, tools, and techniques required for design and development using the AMD Vivado™ Design Suite for FPGAs, SoCs, and adaptive SoCs. The emphasis of this course is on: Introduction to designing FPGAs with the Vivado Design Suite Creating a Vivado project with source files Introduction to the Tcl environment in Vivado and …

Webinar: Basic Booting for AMD Zynq and Versal Devices with Practical Tips and Techniques

Online

Description BLT, an AMD Premier Design Services Partner and Authorized Training Provider, presents this webinar. Are FPGA booting challenges causing frustrating delays and leaving you uncertain about project timelines? Have you spent countless hours wrestling with boot image creation, only to encounter hardware dependencies or secure boot issues that stall progress? Eliminate the guesswork and …

Webinar: Exploring AMD Kria SOM for ROS 2 Multi-Node Communications with TSN Acceleration

Online

Description BLT, an AMD Premier Design Services Partner and Authorized Training Provider, presents this webinar. Unlock the potential of the AMD Kria SOM and discover Time-Sensitive Networking (TSN) benefits for your applications. In this session, you’ll explore the TSN-ROS application and its role in enhancing communications within a TSN framework. Join our hands-on demonstration to …

Webinar: Mastering Clock Domain Crossings (CDC) and Synchronization Techniques

Online

Description Clock domain crossings (CDCs) are a critical aspect of FPGA and embedded system design, and handling them correctly is essential for reliable operation. In this one-hour webinar, we’ll break down CDC fundamentals, explore best practices for managing single-bit and bus CDCs, and demonstrate how to leverage Xilinx Parameterized Macros (XPM) for seamless synchronization. Join …