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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260422T080000
DTEND;TZID=America/Los_Angeles:20260422T090000
DTSTAMP:20260421T163108
CREATED:20260414T062544Z
LAST-MODIFIED:20260414T062544Z
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SUMMARY:Webinar: HDI Design Workflow: From Decisions to Fabrication
DESCRIPTION:Ensure fabrication success with proven HDI design techniques and real-world tools.\nOverview:\n\nAs AI accelerators and edge compute modules push PCB densities to their physical limits\, HDI design has become the defining skill separating production-ready boards from layouts that fail at fabrication. This webinar walks through the complete HDI workflow inside Allegro X using a NVIDIA Jetson-based carrier board. \nYou will learn how to:\n\nArchitect the layer stackup and define blind\, buried and microvia structures\nNavigate fine-pitch BGA breakout routing\nConduct in-design DFM validation to ensure fabrication success\n\nAttendees will leave with a clear\, process-driven understanding of how HDI design decisions are made in real tools on real hardware and learn how to validate those decisions before a board ever reaches a fabrication house. \n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-hdi-design-workflow-from-decisions-to-fabrication/
LOCATION:Online
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/04/Screenshot-2026-04-13-232509.png
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260428T090000
DTEND;TZID=America/Los_Angeles:20260428T100000
DTSTAMP:20260421T163108
CREATED:20260410T023253Z
LAST-MODIFIED:20260410T023253Z
UID:368275-1777366800-1777370400@semiwiki.com
SUMMARY:Webinar: Marvell: Accelerating Interposer Design with Early Signal Integrity Analysis
DESCRIPTION:In this webinar\, Marvell will present how its team accelerates passive interposer routing for advanced 2.5D/3.5D multi die designs by bringing early\, physics based signal integrity feedback into each routing iteration. Rather than relying on repeated\, compute intensive 3D FEM cycles during development\, Marvell uses a Method of Moments (MoM) early SI check available within Synopsys 3DIC Compiler to evaluate routing with real parasitics and simulation data\, fast enough to support rapid iteration and safer exploration of auto routing strategies.  Marvell will also share practical correlation takeaways\, where MoM tracks FEM strongly and where additional margin and correlation work may be needed ahead of final signoff. \nWhat you’ll learn \n\nWhy traditional interposer SI signoff can become a major schedule bottleneck\nHow early SI analysis with MoM differs from FEM and where it fits best\nHow to use physics-based SI feedback during interposer routing iterations\nWhen and how to correlate early SI results with FEM for confidence and margin\nHow early SI enables faster convergence and broader design space exploration\n\n\n\n\n\nFeatured Speakers\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nNitin Navale \nSenior Principal CAD Engineer\, Marvell \nNitin Navale currently serves as 3DIC Methodology Lead at Marvell Semiconductor. He previously worked at AMD & Xilinx for nearly 20 years\, where he contributed to CAD & Methodology across a wide range of disciplines spanning 3DIC\, Signoff\, RTL/Netlisting\, and Physical Verification. Nitin earned his BS and MS in Electrical Engineering from the University of Illinois\, Urbana-Champaign. Outside work\, he is consumed by his devotion to gaming\, strategy\, and music. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nAdish Mehta \nSenior Staff Engineer\, Marvell \nAdish Mehta is a seasoned semiconductor professional specializing in EM/IR signoff\, power integrity\, and signal electromigration analysis for advanced SoC and multi-die designs. He has led the development of scalable\, hierarchical\, and in-context signoff methodologies that improve reliability and design efficiency across bleeding-edge technology nodes. Adish frequently collaborates with global design teams\, foundries\, and EDA vendors to drive innovation in power and reliability analysis\, helping deliver robust\, production-ready silicon across a variety of platforms. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-marvell-accelerating-interposer-design-with-early-signal-integrity-analysis/
LOCATION:Online
ATTACH;FMTTYPE=image/webp:https://semiwiki.com/wp-content/uploads/2026/03/Synopsys-Reports-Record-Quarterly-Revenue-for-Q1-FY-2024.webp
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260429T070000
DTEND;TZID=America/Los_Angeles:20260429T080000
DTSTAMP:20260421T163108
CREATED:20260414T051207Z
LAST-MODIFIED:20260414T051207Z
UID:368340-1777446000-1777449600@semiwiki.com
SUMMARY:Webinar: Application-Specific Processors (ASIPs) for Physical AI
DESCRIPTION:Physical AI is increasingly popular in applications requiring real-time decision making and autonomous operation.  Different from NPUs for cloud platforms\, Physical AI processors can be made application-specific.  By jointly tuning their ISA and memory architecture to the network models required by the application\, power consumption and silicon area are drastically reduced. \nSynopsys ASIP Designer is the industry-leading tool to explore\, design\, and optimize application-specific instruction-set processors (ASIPs)\, including custom NPUs for physical AI. \nIn this Synopsys webinar\, we present the design of “SmarT”\, an ASIP with a RISC-V ISA augmented with specialized vector units for convolutions and quantization\, with 64 MACs. It supports circular gather/scatter addressing of vector data in parallel with computations. Low-overhead DMA moves data blocks from external to local memory. \nNext\, we present a multi-core RISC-V based accelerator for hyperdimensional computing\, designed with ASIP Designer by TU Munich. It applies near-memory computing (NMC) to minimize power consumption and memory bandwidth. This 5-core chip is the first university-led tape-out in Germany using TSMC 7nm technology. \nLearn about: \n\nSynopsys ASIP Designer\, the industry-leading tool to explore\, design and optimize application specific processors\nASIP Design methodologies to address challenges in jointly optimizing the memory architecture and the computational resources for Physical AI architectures\nTwo ASIP designs examples with customize memory architectures for Physical AI applications\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nFeatured Speaker\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nDr. Falco Munsche \nTechnical Product Marketing\, Synopsys \nFalco Munsche is the Technical Product Manager for ASIP design tools at Synopsys. Previously he worked for a total of 20 years as Application Engineer and Software Engineer of ASIP design tools for Synopsys and CoWare\, and as a Design Consultant for Synopsys. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nProf. Hussam Amrouch \nTechnical University of Munich\, Germany \nHussam Amrouch is Professor heading the Chair of AI Processor Design within the Technical University of Munich (TUM). He is the head of Brain-inspired Computing at the Munich Institute of Robotics. Further\, he is the head of the Semiconductor Test and Reliability at the University of Stuttgart. He is the Academic Director of TUM Venture Labs. He is Founding Director of the Munich Advanced-Technology Center for AI Chips (MACHT-AI). \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-application-specific-processors-asips-for-physical-ai/
LOCATION:Online
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/04/Synopsys-ASIP-webinar-800x800-2.png
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260430T090000
DTEND;TZID=America/Los_Angeles:20260430T100000
DTSTAMP:20260421T163108
CREATED:20260408T195314Z
LAST-MODIFIED:20260408T195314Z
UID:368236-1777539600-1777543200@semiwiki.com
SUMMARY:Webinar: Powering 3D Multi-Die Designs with RedHawk-SC Electrothermal
DESCRIPTION:As semiconductors continue to scale\, designers are turning to 3DIC architectures to meet increasing demands for performance\, energy efficiency\, and functional density in data centers and edge AI applications. However\, stacking multiple dies introduces new multiphysics challenges including electrical\, structural\, and thermal issues. Join this webinar to learn how RedHawk-SC Electrothermal enables designers to analyze the multiphysics behavior of chips all at once in complex multi-die designs. \nTogether\, Synopsys and Ansys\, part of Synopsys\, provide engineers a comprehensive flow that offers in-design analysis along with final signoff\, enabling faster and more confident development of next-generation multi-die designs. \nAttend this webinar to:  \n\nEnhance your understanding of RedHawk-SC Electrothermal as a foundry-certified multiphysics integrity tool for multi-die designs\nLearn about new features and flow capabilities for 2.5D/3D thermal and mechanical analysis\, including GPU acceleration and ML-based solver\nIntegration of multiphysics simulation in Synopsys implementation and signoff solutions\n\n\n\n\n\nFeatured Speaker\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nDr. Lang Lin \nProduct Management\, Principal \nDr. Lang Lin\, Product Management\, Principal \nBio: Dr. Lang Lin is a technology leader at Synopsys Inc.\, where he directs product strategy for EDA solutions that ensure the multiphysics integrity\, reliability\, and security of advanced IC and multi die systems. With a Ph.D. in Electrical and Computer Engineering from the University of Massachusetts\, his background spans low power design\, multi-die design\, and hardware security—areas that continue to influence his work at the intersection of multiphysics modeling and secure silicon design. Dr. Lin has co authored over 40 papers and patents\, and his work has been recognized with top honors including IEEE HOST Best Paper Award\, IEEE DAC Best Paper Award\, and the Ansys CEO Innovation Award. He worked for Intel and Ansys before his product management role at Synopsys. \nProfile: Lang Lin | Synopsys \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-powering-3d-multi-die-designs-with-redhawk-sc-electrothermal/
LOCATION:Online
ATTACH;FMTTYPE=image/jpeg:https://semiwiki.com/wp-content/uploads/2026/04/Synopsys-RedHawk-SC-Electrothermal-3DIC-webinar-1200x1200px-v1A-2.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260506T080000
DTEND;TZID=America/Los_Angeles:20260506T090000
DTSTAMP:20260421T163108
CREATED:20260420T073725Z
LAST-MODIFIED:20260420T073725Z
UID:368582-1778054400-1778058000@semiwiki.com
SUMMARY:Webinar: All in One Bluetooth Audio: A Complete Solution on a TSMC 12nm Single Die
DESCRIPTION:Abstract\n\nDive into the future of Bluetooth audio with Ceva and Dolphin Semiconductor’s breakthrough 12nm Smart Edge AIoT SoC solution. \nThis webinar shows how advanced wireless connectivity\, integrated AI processing\, and premium audio technologies and power management come together to deliver superior performance\, lower power\, and faster time to market. \nLearn how a combined Ceva and Dolphin Semiconductor’s solution turnkey platform enables low power and high performance next generation features: Bluetooth High Data Throughput\, Channel Sounding\, spatial audio\, voice commands\, sensor fusion\, and more. \nIdeal for cutting edge earbuds\, headsets\, smartwatches\, and smart glasses. \nDon’t miss this opportunity to enhance your next audio product with industry leading innovation. \nWhat you will learn in this session:\n\nMap and understand audio peripheral product challenges\, particularly for TWS/OTC\nEvaluate the pros and cons of existing design level solutions\nCeva’s and Dolphin Semiconductor’s solution for overcoming TWS/OTC device challenges\n\n\nTarget Audience\nChip architects & SoC designers\, audio and DSP engineers\, embedded software engineers\, and product managers for hearables & wearables \n\nSpeakers\n\n\n\n\n\n\n\nFranz Dugand \nSr. Director\, Product Marketing\, Ceva \n\n\n\n\n\n\nEtienne Faucher \nProduct line Portfolio Manager – Audio\, Dolphin Semiconductor \n\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-all-in-one-bluetooth-audio-a-complete-solution-on-a-tsmc-12nm-single-die/
LOCATION:Online
ATTACH;FMTTYPE=image/jpeg:https://semiwiki.com/wp-content/uploads/2026/04/CEVA-Dolphin-Weninar-SemiWiki_400x400-v2_260419.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260508T100000
DTEND;TZID=America/Los_Angeles:20260508T110000
DTSTAMP:20260421T163108
CREATED:20260414T062754Z
LAST-MODIFIED:20260414T062754Z
UID:368403-1778234400-1778238000@semiwiki.com
SUMMARY:Webinar: How Data Rates Doubled\, and Where Validation Reaches Its Limit
DESCRIPTION:Data rates have doubled\, but validation methods have not kept pace. As PCIe\, DDR\, and multi-terabit optical interconnects evolve\, engineers are encountering signal integrity challenges much earlier in the design process. \nJoin Niels Fache\, Senior Vice President and General Manager of Design Engineering Software at Keysight\, to explore where validation becomes more challenging as speeds increase\, and how engineering teams are adapting. You’ll learn how simulation\, architecture modeling\, and high-fidelity measurement help validate designs before silicon exists and reduce downstream risk. \nREGISTER HERE
URL:https://semiwiki.com/event/webinar-how-data-rates-doubled-and-where-validation-reaches-its-limit/
LOCATION:Online
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260515T100000
DTEND;TZID=America/Los_Angeles:20260515T110000
DTSTAMP:20260421T163108
CREATED:20260414T062904Z
LAST-MODIFIED:20260414T062904Z
UID:368405-1778839200-1778842800@semiwiki.com
SUMMARY:Webinar: How Frequency Ranges Expanded\, and Why Measurement Fidelity Became Critical
DESCRIPTION:As systems move into higher frequencies and wider bandwidths\, small measurement errors can lead to costly design decisions. Engineers working in wireless\, radar\, satellite\, and optical domains must now validate signals that push existing tools to their limits. \nJoin Jun Chie\, Vice President of Product Management at Keysight\, to explore where measurement fidelity begins to break down\, and how engineers are adapting. You’ll see how next-generation instrumentation helps improve signal accuracy\, reduce uncertainty\, and increase confidence in design decisions. \nREGISTER HERE
URL:https://semiwiki.com/event/webinar-how-frequency-ranges-expanded-and-why-measurement-fidelity-became-critical/
LOCATION:Online
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260522T100000
DTEND;TZID=America/Los_Angeles:20260522T110000
DTSTAMP:20260421T163108
CREATED:20260414T063003Z
LAST-MODIFIED:20260414T063003Z
UID:368408-1779444000-1779447600@semiwiki.com
SUMMARY:Webinar: How System Scale Expanded\, and Why Network Traffic Validation Became Essential
DESCRIPTION:AI data center networks now operate at a scale where device-level validation no longer reflects real performance. Engineers must understand how systems behave under realistic traffic conditions\, not just in isolated tests. \nJoin Ram Periakaruppan\, vice president and general manager of network applications and security at Keysight\, to learn how large-scale traffic emulation reveals congestion\, latency issues\, and performance limits. You’ll see how to validate AI infrastructure under real workloads and ensure it performs reliably at scale. \nREGISTER HERE
URL:https://semiwiki.com/event/webinar-how-system-scale-expanded-and-why-network-traffic-validation-became-essential/
LOCATION:Online
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260529T100000
DTEND;TZID=America/Los_Angeles:20260529T110000
DTSTAMP:20260421T163108
CREATED:20260414T063056Z
LAST-MODIFIED:20260414T063056Z
UID:368410-1780048800-1780052400@semiwiki.com
SUMMARY:Webinar: How Manufacturing Complexity Increased\, and Why Validation Had to Evolve
DESCRIPTION:As semiconductor complexity increases and board designs become denser\, manufacturing teams face tighter tolerances\, reduced test access\, and rising pressure to maintain yield and throughput. Validating RF performance and high-speed digital signal integrity at production scale adds a new layer of complexity that traditional approaches struggle to address. \nJoin Jason Kary\, Senior Vice President and President of Keysight’s Electronic Industrial Solutions Group\, to explore how manufacturing validation is evolving. You’ll learn how wafer-level and in-circuit test strategies improve coverage\, detect defects earlier\, and enable consistent\, high-volume production at scale without compromising quality. \nREGISTER HERE
URL:https://semiwiki.com/event/webinar-how-manufacturing-complexity-increased-and-why-validation-had-to-evolve/
LOCATION:Online
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