Description We’ll dive into one of the most pressing questions in the community: Are physical attacks practical against post-quantum schemes in the real world? If yes, how to harden the …
Continue reading "Webinar: Securing Post-Quantum Implementations Against Physical Attacks"
Thursday, July 10, 2025 10:00am PDT | 1:00pm EDT | 19:00 CEST As AI revolutionizes industries, the demand for high-performance, low power computing intensifies, placing unprecedented requirements on data centers. This panel …
Continue reading "Webinar: Data Center RAS in the Age of AI Computing"
Abstract As AI workloads increasingly dominate numerous cloud and edge applications, building a scalable, efficient, and future-ready AI chips is no longer optional—it's essential. This webinar explores the latest AI …
Continue reading "Webinar: What it really takes to build a future-proof AI architecture?"
*WORK EMAIL IS REQUIRED* As data volumes surge across cloud, AI, automotive, and edge systems, efficient lossless compression has become essential for meeting performance, latency, and bandwidth constraints. This webinar …
This online workshop introduces key concepts, tools, and techniques required for design and development using the AMD Vivado™ Design Suite for FPGAs, SoCs, and adaptive SoCs. The emphasis of this course is …
Continue reading "Vivado Quick Start with Versal Devices Workshop"
Description BLT, an AMD Premier Design Services Partner and Authorized Training Provider, presents this webinar. Are FPGA booting challenges causing frustrating delays and leaving you uncertain about project timelines? Have …
Designing DSP Applications with Versal AI Engines Workshop This workshop covers the AMD Versal AI Engine architecture and using the AI Engine DSP Library, system partitioning, rapid prototyping, and custom coding of …
Continue reading "Designing DSP Applications with Versal AI Engines Workshop"
Description BLT, an AMD Premier Design Services Partner and Authorized Training Provider, presents this webinar. Join us to explore the functionality and configurability of the AMD Zynq UltraScale+ RFSoC. With …
Continue reading "Webinar: Maximizing RFSoC Potential with Functionality and Configurability"
Accelerating Connectivity with the Versal Adaptive SOC Network on Chip Workshop This workshop introduces the AMD Versal network on chip (NoC) to users familiar with other SoC architectures. Besides providing …
Continue reading "Accelerating Connectivity with the Versal Adaptive SOC Network on Chip Workshop"
Description BLT, an AMD Premier Design Services Partner and Authorized Training Provider, presents this webinar. When it comes to embedded software development, managing multiple tools, maintaining version control, and navigating …
Continue reading "Webinar: Getting Started with the Vitis Unified IDE"
Achieving Timing Closure in FPGA Designs Workshop Do you find it challenging to close timing in your FPGA design? This workshop will guide you through leveraging AMD Vivado’s tools, optimizing your design, and applying best practices for static timing analysis to achieve reliable timing closure. Gain hands-on experience with timing closure techniques and learn strategies to improve …
Continue reading "Achieving Timing Closure in FPGA Designs Workshop"
Description BLT, an AMD Premier Design Services Partner and Authorized Training Provider, presents this webinar. Unlock the potential of the AMD Kria SOM and discover Time-Sensitive Networking (TSN) benefits for your applications. In this session, you’ll explore the TSN-ROS application and its role in enhancing communications within a TSN framework. Join our hands-on demonstration to …
From Theory to Practice: Applying Timing Constraints Workshop Do you struggle to identify which constraints are needed for a design or how to properly input them? This workshop will cover how to use features in Vivado, clock domain crossing strategies, and how to get the most out of static timing analysis for Versal devices. This …
Continue reading "From Theory to Practice: Applying Timing Constraints Workshop"
Description Clock domain crossings (CDCs) are a critical aspect of FPGA and embedded system design, and handling them correctly is essential for reliable operation. In this one-hour webinar, we’ll break down CDC fundamentals, explore best practices for managing single-bit and bus CDCs, and demonstrate how to leverage Xilinx Parameterized Macros (XPM) for seamless synchronization. Join …
Continue reading "Webinar: Mastering Clock Domain Crossings (CDC) and Synchronization Techniques"
Essential Debugging Techniques Workshop This workshop is for hardware engineers, system architects, and anyone who wants to learn best practices for debugging challenging issues encountered while developing FPGAs, SoCs, PCBs, and embedded systems using the Vivado Design Suite. The features and capabilities of the Vivado Integrated Logic Analyzer are covered in lectures and demonstrations, along with …
