Looking Forward to ICCAD 2021 As ICCAD 2021's general chair, please let me announce that the main technical program of the 40th anniversary of ICCAD will take place purely virtual from November 1st (until November 4th) 2021, which is due to the ongoing pandemic situation. Thanks to the rapidly deployed vaccines and strict hygienic measures, ICCAD …
Web Summit brings together the people and companies redefining the global tech industry. Web Summit will return to Lisbon this year. Join us in November. PRE-REGISTER FOR 2021 We’re a company from Dublin, Ireland, that holds events across the world: Web Summit in Lisbon and Tokyo, Collision in Toronto, and RISE in Kuala Lumpur. …
Taming the Challenges of Advanced Node Digital Designs November 10, 2021 Overview Although new challenges arise with each node, the move from bulk technologies to advanced node technologies marks a distinctive shift in complexity. Some of the important factors to consider are new devices, challenging and competing design rules, double patterning, managing of the layout …
Continue reading "CadenceTECHTALK: Taming the Challenges of Advanced Node Digital Designs"
Wednesday, November 10, 2021 | 10:00-10:40 a.m. PST Analog designers appreciate the importance of tight communication between layout and design teams, yet with geographically dispersed teams this can be a big challenge. Close collaboration between circuit designer and layout designer is essential for creating high-quality analog layouts. With this close connection and sharing feedback in …
Learn how Ansys tools can model the physics governing the behavior of synchronous machines and assist developers in optimizing tuning parameters, e.g., geometry, material selection and the machine’s feeding. Time: November 10, 2021 9 AM EST / 2 PM GMT / 7:30 PM IST Venue: Online About this Webinar From washing machines to elevators. From …
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Time: November 10, 2021 11 AM EST / 4 PM GMT / 9:30 PM IST Venue: Online About this Webinar Imagine 3D printing a part and hearing ‘oops’ from your operator or engineer. What’s the first thing that goes through your mind?...How much is this going to cost us? Whether you’re producing parts out of …
A Digital Event - November 10-11 Ready to share and discuss the latest design and verification best practices with your peers from around the world? It’s time for our annual JasperTM User Group Conference, held on November 10 and 11 this year. This in-depth technical conference connects designers, verification engineers, and engineering managers from around the …
An presentation of my latest book as part of the IEE USA webinar series
Tuesday, November 11, 2021 | 10:00-10:30 a.m. PST Testing an O-RAN Radio Unit (O-RU) SoC at full scale implies sending realistic traffic, in conformance with current specifications and at the right time on the right interfaces to simulate complex scenarios and cover as many corner cases as possible. It requires a robust debug methodology which …
Continue reading "What’s Needed to Perform End-to-End Testing for 5G Open Radio Access Network SoCs"
This talk will highlight the high-profile challenges faced by engineers while designing and analyzing hypersonic vehicles. Learn about Ansys’ computational fluid dynamics (CFD) simulation technologies that can address these challenges. Time: November 17, 2021 1 AM EST / 6 AM GMT / 11:30 AM IST Venue: Online About this Webinar There has been surge of …
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Wednesday, November 17, 2021 | 10:30-11:30 a.m. PST In the latest generation of multiple processor SoCs, designers are adding cache-coherent agents beyond the multi-processor clusters, making it a complex verification challenge. System coherency needs to be maintained at various levels, beginning at the cluster level, and continuing, across the cache coherent interconnect and across chips …
Welcome to SAFE™ (Samsung Advanced Foundry Ecosystem) Forum 2021. Since 2018, Samsung Foundry has been operating the foundry ecosystem program called SAFE™ (Samsung Advanced Foundry Ecosystem) to ensure deep collaboration between ecosystem partners and customers and deliver competitive and robust System on Chip (SoC) designs based on IP (Intellectual Property), EDA (Electronic Design Automation), Cloud, …
Power and Energy Optimization Using Tensilica IP November 17, 2021 Overview Design teams are facing the challenges of having to add more and more processing and programmable capabilities in their SoC in order to adapt and implement the latest and greatest algorithms during the lifecycle of their products, but at the same time comply with …
Continue reading "CadenceTECHTALK: Power and Energy Optimization Using Tensilica IP"
Silicon Desert—An Oasis of Innovation Since the early 1950’s, Arizona has been an oasis in the desert for tech companies, with many established names making their home here. Today, with the recent enactment of the Creating Helpful Incentives to Produce Semiconductors—CHIPS for America Act, aimed at incentivizing U.S. semiconductor technology leadership and manufacturing, strengthening supply …
