Webinar: Tackling Emerging DFT Verification Challenges with Questa One
June 12 @ 8:00 AM - 9:00 AM
Rising semiconductor complexity—driven by multi-die architectures, the move towards more advanced technology nodes, and more stringent reliability targets, is dramatically increasing the volume of verification required to achieve DFT verification sign-off.
Come learn how the Questa One DFT Verification solution, combined with Tessent Silicon Lifecycle Solutions delivers an evolution in user experience and performance to address these emerging verification challenges.
What You Will Learn:
- Latest DFT-aware Questa One methodologies and engines tailored to Tessent workflows
Who Should Attend:
- Verification engineers and managers responsible for verification of Design for Test implementations.
Products Covered:
- Questa One Sim
- Questa One Sim FX
- Questa One SFV
Speaker:
Jake Wiltgen
Solutions Director, Siemens EDA
Jake Wiltgen is a Solutions Director at Siemens, responsible for divisional strategy in DFT Verification, Automotive, Functional Safety, 3DIC, Rad-Hard, and High-Performance Compute markets across the digital verification technologies portfolio.
Moreover, Jake serves as the co-chair of the Front-End Design Track for the prestigious Digital Automation Conference (DAC) and is a primary representative for Siemens EDA in numerous automotive and functional safety standardization initiatives within Accellera and IEEE.
He holds a Bachelor of Science degree in Electrical and Computer Engineering from the University of Colorado Boulder. Prior to Siemens, Jake held various design, verification, and leadership roles within IC and SOC development teams at Xilinx, Paneve, Micron, and Broadcom.
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