Webinar: Application-Specific Processors (ASIPs) for Wireless Communication SoCs
May 21 @ 7:00 AM - 8:00 AM
Featured Speakers:
- Dr. Falco Munsche, Technical Product Marketing, Synopsys
- Junsu Heo, SoC Design Lab, Konkuk University, Korea
Learn about:
- Synopsys ASIP Designer, the industry-leading tool to explore, design and optimize application-specific processors
- ASIP design methodology to address challenges in modern wireless communication systems
- Several ASIP designs crafted with the tool, including ASIPs for FFT, channel estimation, MIMO sphere decoding, and LDPC-based channel coding.
Abstract
The successful switch from 4 to 5G required rethinking important architectural concepts in wireless SoCs. The traditional split between general-purpose programmable processors (primarily for MAC and higher-level protocols) and hardwired datapaths (primarily for digital front-end and baseband processing) no longer holds. Designers bring into play Application-Specific Processors (ASIPs), to meet 5G’s high data rates and low latency requirements with low power consumption, while maintaining software programmability to quickly adapt to and deploy new functionality. 5G SoCs may contain a multicore ASIP configuration, with different ASIPs customized to implement specific parts of the 5G block diagram, such as FFT, channel estimation and equalization, interleaving, or channel coding. The individual ASIPs may exhibits high amounts of instruction-level and data-level (SIMD) parallelism with specialization of functional units and memory architecture.
Synopsys’ ASIP Designer tool enables customers to explore, design and optimize differentiating ASIP architectures for 5G and beyond in very short time, in both mobile systems and base stations.
Featured Speakers
Technical Product Marketing, Synopsys
Falco Munsche is the Technical Product Manager for ASIP design tools at Synopsys. Previously he worked for a total of 20 years as Application Engineer and Software Engineer of ASIP design tools for Synopsys and CoWare, and as a Design Consultant for Synopsys. He holds a Ph.D. (2002) and Dipl-Ing. degree (1995) in Electrical Engineering from RWTH Aachen University.
SoC Design Lab, Konkuk University, Korea
Junsu Heo received the M.S. degree in electronics engineering from Konkuk University, Seoul, South Korea, in 2023, where he is currently pursuing the Ph.D. degree in electronics engineering. His research interests include the modeling and simulation for SoC architecture and the algorithm-architecture co-design for hardware accelerators including ASIPs.
Emerging NVM Technologies: ReRAM Gains Visibility in 2024 Industry Survey