Siemens Calibre Seminar

June 24, 2025

12:00 PM -1:00 PM

Moscone West | San Francisco, CA

Calibre: Supercharge your chip integration efforts

Siemens is excited to host an exclusive event for our customers at the Design Automation Conference

Join us at DAC for lunch and learn how our new products can supercharge your chip integration efforts:

– Chip design bottleneck: Millions of violations overwhelm teams.
– Traditional tools lag behind: Engineers waste hours manually debugging.
– Benefits: Rapid loading & navigation. AI/ML-powered violation clustering for faster fixes.
– Seamless workflow integration: Works with layout viewers & place-and-route tools. Enables direct fixes within the design environment.
– Boosted collaboration: Shareable bookmarks & block-level results. Breaks down silos for smoother teamwork.

Who should attend:

– Full chip integration engineers
– SoC engineers
– Digital designers
-Physical verification engineers
– Managers of the above

REGISTER HERE