CadenceTECHTALK: High Performance Hierarchical IR Signoff for Large SoCs and 3D-ICs

IR signoff for advanced SoCs and 3D-ICs is a major challenge due to extremely large and complex power networks that can exceed 100 billion nodes. Designers are faced with very long runtimes and very large compute resource requirements amounting to thousands of CPUs and 100TB+ memory to run a full-chip flat.

In this webinar, you will learn how Voltus XM technology addresses this daunting IR signoff challenge. We will present a bottom-up and top-down hierarchical methodology that ensures accurate IR closure at both sub-chip and SoC level. The talk will demonstrate how to build models to be used for top-level analysis and how to use boundary voltage flow for accurate sub-chip signoff.  With this new innovative approach, designers can see up to 10X reduction in runtime and compute resource requirement.

What You’ll Learn:

• How Voltus XM technology addresses IR signoff challenges
• A hierarchical methodology that ensures accurate IR closure at both sub-chip and SoC level
• How to build models for top-level analysis and use boundary voltage flow for accurate sub-chip signoff