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Ansys ASEAN Semiconductor Virtual Summit 2025
May 15 @ 2:30 PM - 5:30 PM
Join the Ansys ASEAN Semiconductor Virtual Summit 2025 to explore the latest in semiconductor design, industry best practices, enhancing your skills, and shape the future of technology. Don’t miss it!
DATE/TIME:
May 15, 2025
2:30 PM SGT (Singapore Time), 1:30 PM ICT (Vietnam Time)
Venue:
Virtual
Overview
Join us for the Ansys ASEAN Semiconductor Virtual Summit 2025 — a place to catch up on the latest Semiconductor design advances and industry best practices. This virtual summit will explore future trends with keynotes from industry leaders and offer technical insights from Ansys domain experts and chip designers from the world’s top semiconductor companies. At this premier conference, you will:
- Discover key insights: Learn cutting-edge techniques and strategies for on-chip power integrity and reliability signoff for digital SoCs and analog mixed signal designs from Ansys and industry experts
- Explore multiscale multiphysics challenges: Dive into complex power, thermal, and signal integrity (PI/TI/SI) Signoff topics, including multiscale, multiphysics simulations essential for 2.5D/3DICs designs and heterogeneous integration
- Accelerate Innovation: Gain valuable knowledge on how advanced chip-package-system simulation technologies can streamline design processes and drive innovation
- Network with experts: Connect with Ansys experts to explore new opportunities for collaboration
Ansys ASEAN Semiconductor Virtual Summit is your opportunity to deepen your understanding of power-noise-reliability sign-off for chip-package systems, enhance your skills, and advance your engineering capabilities. Don’t miss this chance to be part of the conversation shaping the future of technology.
Agenda
| Time (SGT) | Title |
| 2:30 pm – 2:35 pm | Welcome Note by Ansys |
| 2:35 pm – 2:55 pm | Industry Keynote |
| 2:55 pm – 3:15 pm | Ansys Keynote |
| 3:15 pm – 3:35 pm | Latest Trends in Chip-Package-System Co-Simulation |
| 3:35 pm – 3:55 pm | Digital SoC Power Integrity Sign-off – Challenges and Solutions |
| 3:55 pm – 4:00 pm | Break |
| 4:00 pm – 4:10 pm | Industry Expert Talk – SoC PDN Signoff |
| 4:10 pm – 4:30 pm | Power Integrity and Reliability signoff for Analog Mixed Signal Designs |
| 4:30 pm – 4:40 pm | Industry Expert Talk – AMS IP EM/IR Signoff |
| 4:40 pm – 5:00 pm | 3DIC Systems – Power, Signal and Thermal Integrity |
| 5:00 pm – 5:15 pm | Fireside chat – 3DIC and AI/ML Megatrends in PDN Signoff |
| 5:15 pm – 5:20 pm | Concluding Remarks |
What attendees will learn
- SoC Power-Integrity and Reliability Sign-off
- 2.5D/3DIC Interposer – Power, Signal, Thermal Integrity
- Analog & Mixed-Signal Designs Power and Reliability
- Advanced Power Integrity flows: Sigma-DvD, ROM, IR-ECO, etc.
- Reliability Analysis: Electromigration, ESD, Thermal
- Shift-left / In-design Analysis and Optimization
- Chip-Package-System Co-simulation
- Chip-Aware Package Design and Package-Aware Chip Design
Who should attend
- Company Leaders
- Solution architects.
- Design Engineering Directors
- Design Engineering Managers, Team Leads
- Chip-Package-System Power Integrity and PDN/EMIR Experts
- Digital IC Design Engineers
- Analog Mixed Signal Design and Layout Engineers
- Semiconductor design professionals
- Academia
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