AI-Powered Waveform Debugging: Revolutionizing Semiconductor Verification

On July 9, 2025, a DACtv session with Zackary Glazewski of ChipAgents AI introduced Waveform Agents, an AI-driven solution by Chip Agents designed to tackle the complex challenge of waveform debugging in semiconductor design. The speaker highlighted the difficulties of traditional waveform debugging and demonstrated how AI agents, leveraging large language models (LLMs), offer a scalable, autonomous approach to streamline verification, addressing the “needle in a haystack” problem inherent in analyzing massive waveform datasets.

Waveform debugging is notoriously challenging due to the sheer volume of data involved, often ranging from tens of gigabytes to terabytes in large systems. Bugs typically manifest within a narrow temporal range, making their identification akin to finding a needle in a haystack. Beyond localization, fixing these bugs requires deep knowledge of signal interactions, their roles in design and testbench files, and their interconnections. This dual challenge—locating and resolving issues—demands significant time and expertise, as engineers must navigate intricate relationships and interpret signal behaviors.

Traditional methods fall short in addressing these issues. Waveform viewing software, while useful for visualizing signal toggles and protocols, struggles with the scale of modern datasets, requiring engineers to manually comb through vast amounts of data. Signal tracing features, though helpful, rely heavily on engineer guidance, adding to the time-intensive process. Anomaly detection using traditional machine learning can identify patterns but lacks flexibility for novel issues, as it depends on pre-trained datasets that may not cover new anomalies. Formal tools, while powerful for finding counterexamples, do not scale well for large systems and still require manual effort to pinpoint and fix errors.

Waveform Agents, powered by LLMs, offer a transformative solution by autonomously handling end-to-end waveform debugging. Unlike traditional LLMs that process entire datasets and risk exceeding context limits, these agents employ intelligent context selection. They traverse design and testbench files, log files, and waveforms, selectively analyzing relevant data to identify bugs without overwhelming computational resources. This approach ensures scalability and efficiency, even for terabyte-scale datasets. The agents can detect a wide range of issues, from functional failures to assertion violations, whether in the design or testbench, without requiring specific error syntax or predefined signatures.

The process begins with the agent analyzing regression logs and waveforms to localize bugs, leveraging its pre-trained understanding of the codebase and specifications. It then proposes fixes by interpreting signal relationships and referencing design intent, reducing the need for manual intervention. For instance, in a regression with thousands of tests, the agent autonomously parses logs, identifies failure signatures, and maps them to specific design or testbench issues, eliminating the need for repeated training per project. This pre-trained model adapts dynamically, pulling relevant context as needed, ensuring flexibility across diverse scenarios.

The benefits are significant: Waveform Agents drastically reduce debugging time, enhance scalability, and improve accuracy by understanding complex signal interactions. By automating both bug localization and resolution, they free engineers from tedious manual tasks, allowing focus on higher-value design work. The session addressed concerns about context limits, with the speaker noting that intelligent context selection avoids processing entire waveforms, making the solution practical for real-world applications.

Chip Agents’ approach marks a paradigm shift in verification, aligning with the industry’s need for smarter, data-driven tools to handle growing design complexity. By integrating AI into waveform debugging, Waveform Agents promise to accelerate verification cycles, improve first-time silicon success rates, and empower engineers to tackle the challenges of modern semiconductor design with greater confidence and efficiency.

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