Circuit Simulation and IC Layout update from Mentor at DAC

Intro
On Monday evening I talked with Linda Fosler, Director of marketing for the DSM Division at Mentor about what’s new at DAC this year in circuit simulation and IC layout tools.

Notes
IC Station – old name for IC layout tools

Eldo – Eldo Classic- Cell characterization
– ST is the early customer and teaching customer, their Golden Simulator
– Widely deployed worldwide

Eldo Premier (January 2011 introduced, free transition from Eldo customers, new option, uses 2X the licenses) – Multi core, multi cpu
– Accuracy driven
– More accurate than Berkeley (they focus on PLL)
– FineSim from Magma
– XA from Synopsys
– Developed in Grenoble, all new kernel, native MT
– Average of 2.5X faster than Eldo at same accuracy, up to 20x faster
– Input netlists: Eldo, HSPICE
– Some analysis missing in Premier and will be released in next 12 months
– DAC Session at 9AM on Tuesday AM

ADiT – Fast SPICE simulator- Analog blocks up to 50 Million devices
– Adding new capabilities
– MediaTek standardized on ADiT
– Similar to other Fast SPICE tools
– Macro tuning capability and new partitioning in development

Questa ADMS – Single kernel AMS simulator- Number one or two market share per EDAC, Gary Smith EDA
– Close to Cadence in market share

Grenoble – Eldo/Eldo Premier R&D
Taiwan – ADiT team/Design Kits
Armenia – CICD R&D
Cairo – models, PDK
Fremont – Division Headquarters
Wilsonville – Custom IC Design R&D
Austin – Custom Router R&D

Innovate In IC physical design, stay close to silicon design.

Technical Advisory Board – multiple initiatives
– Quarterly meetings
Simulators – all work within Cadence Virtuoso (Artist Link)

Analog within Intel microprocessors

Challenges
– Variability (Physical, Electrical)
– Design Risk, AMS is 75% of the risk for failure and cost for design and verification
– Need MS verification (SPICE, HDL, Analog HDL, RTL)
– Questa AMS (Analog Real Number modeling)

Questa ADMS – C/C++, Matlab, VHDL-AMS, …

IC Station (Version 9) – New name is: Pyxis Custom IC Platform (Version 10)

Pyxis – OA database compliant (available now)
– OA native for some functions
– Schematics, Layout, Floorplanning
– Launch simulators
– Concurrent design, multiple designers can edit in the sam cell at the same time
– Custom router
– Multiple designers can edit in the same cell at the same time
– Interface with Clio Soft
– Can be used on LAN, not so tested on WAN yet
– Custom Router (Native OA), easily go back and forth
o Transistor, Cell, Block, Chip, Proven (Used at Marvell) [not related to Olympus – big digital, different division]
o Interactive or batch routing
o Uses Calibre RealTime deck, good integration

Design Kits – founding member of IPL
– Part of Open PDK
– Can help to translate Development Kit formats
– Pcell translator: Robust, accurate, fast (1 foundry, 1 customer using it too)
– Create new PDK’s in a few weeks, able to QA libraries quickly

Summary
Mentor updates their tools for IC layout through the Pyxis acquisition and enhances circuit simulation with a speedier Eldo Premier. AMS co-simulation between HDL and SPICE simulators is a strong point for Mentor.