Liberty IP Excellence: Building a Robust Verification Framework for Automotive IPs

As 2025 draws to a close, the semiconductor industry continues to push boundaries, particularly in automotive applications where reliability is non-negotiable. At the TSMC Open Innovation Platform forum this year, a collaborative presentation by NXP Semiconductors and Siemens EDA stood out: “Liberty IP Excellence: Building a Robust Verification Framework for Automotive IPs.” Presented by Santhosh K, Khushboo R, Pramod G from NXP, alongside Ajay Kumar and Ray Valencia from Siemens EDA, this talk highlighted the critical role of Liberty files in SoC design and proposed innovative quality assurance (QA) methodologies to ensure flawless IP delivery.

The motivation stems from the foundational IPs (standard cells, memories, IOs) that form the backbone of System-on-Chip designs. Liberty (.lib) files serve as the industry standard for encapsulating timing, power, noise, and more, including advanced features like statistical variation and waveform data for sub-10nm nodes. NXP, a pioneer in automotive semiconductors, emphasizes uncompromising quality to meet the sector’s stringent demands. Early QA in their flow minimizes costs, time, and resources, but Liberty’s complexity encompassing aspects like Liberty Variation Format (LVF) for statistical data and Composite Current Source (CCS) for timing, noise, and power—poses significant challenges. Interpreting these files manually is error-prone, and inaccuracies can cascade into design failures, especially in safety-critical automotive systems.

The proposed methodology embeds advanced verification tools into NXP’s QA flow, leveraging Siemens’ Solido Analytics for AI-driven error detection, analysis, and comparison. This solution enables full automation, easing adoption for Liberty users while saving engineering and compute resources. It targets advanced nodes, focusing on LVF and CCS to ensure design reliability.

Diving into NXP’s QA flow analysis, the presentation detailed several key components. First, outlier detection using AI identifies anomalies in Liberty data that deviate from neighboring values, such as slew/load points within tables or across Process-Voltage-Temperature (PVT) conditions. Siemens Solido Analytics employs machine learning models to sweep dimensions like transitions, constraints, temperature, voltage, and custom sweeps (e.g., cell drive strength). Users set tolerance thresholds, triggering alerts for outliers, which could indicate characterization issues.

Version-to-version comparison addresses common scenarios like PDK revisions, design spec changes, or legacy setup recreations. The flow uses plotting for rapid visualization and interpolates tables for fair, apples-to-apples assessments, accelerating correlation and reducing manual effort.

Another pillar is CCS versus Non-Linear Delay Model (NLDM) verification. CCS captures timing in the current domain, while NLDM uses voltage; mismatches signal incorrect settings. The methodology converts CCS data to the voltage domain for direct comparison, ensuring consistency.

LVF and LVF Moments checks tackle the complexity of statistical characterization. Nominal Liberty characterization takes hours, but LVF—requiring up to five additional statistical measures—can extend to weeks or months. LVF formats include 1-sigma early/late (typically 3-sigma/3, representing Gaussian distributions) and Moments (mean shift, skewness, standard deviation) for complex distributions. On-chip variation is crucial for nodes ≤20nm, where inaccurate LVF can cause 50-100% timing deviations. Automated checks detect outliers in LVF groups and recreate sigma tables from Moments for matching; discrepancies highlight inconsistencies.

Finally, Power-Performance-Area (PPA) analysis enables early library comparisons across technologies. With thousands of cells and varying formats, traditional methods delay insights until later design phases like synthesis or P&R. The proposed heuristics align data by cell/pin names, functionalities, and table indices, revealing trends like performance versus drive strength (e.g., Dataset A buffers outperforming B at drives >3) or power consumption (e.g., Dataset A flip-flops superior across drives).

Bottom line: this embedded solution delivers comprehensive QA for automotive libraries, including impact analysis across PDK revisions, automated execution, LVF validation, outlier detection, CCS-NLDM alignment, and full coverage. NXP achieved 2x efficiency gains: for trends and validation on 1000 cells across 25 PVTs, runtime dropped from 10 to 5 units; impact analysis (6 PVTs) from 5 to 3 units; PPA comparison (4 PVTs) similarly improved. This collaboration exemplifies 2025’s tech ethos—AI-augmented precision amid escalating complexity—paving the way for safer, more efficient automotive semiconductors.

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