Key Takeaways
- AI is transforming semiconductor design verification, addressing challenges like complexity, time constraints, and resource scarcity that traditional methods cannot handle.
- In 2024, only 14% of chips achieved first-time silicon success, with 75% behind schedule due to tight time-to-market pressures and a critical shortage of skilled professionals.
- The speaker introduced the 'Costa One' AI-driven approach, which enhances verification through connected workflows, data-driven insights, and scalable tools in specification generation, debugging, and coverage analysis.
- AI tools automate specification generation, transform regression testing, and improve coverage analysis, significantly reducing manual effort and debugging time while providing actionable insights.
- The semiconductor market is projected to exceed a trillion dollars by 2030, with generative AI expected to grow rapidly, reshaping infrastructure and services in the industry.
In a DACtv session on July 9, 2025, Abhi Kolpekwar, Vice-President & General Manager at Siemens EDA, illuminated the transformative role of artificial intelligence (AI) in addressing the escalating challenges of semiconductor design verification. The presentation underscored the limitations of traditional methods and introduced a smarter, AI-driven approach to enhance efficiency, scalability, and insight in the verification process.
The semiconductor industry is grappling with unprecedented complexity. In 2024, only 14% of chips achieved first-time silicon success, highlighting the difficulty in managing intricate designs. Additionally, 75% of chips are behind schedule due to tight time-to-market pressures, compounded by a critical shortage of skilled professionals, with 80% of the industry’s demand for talent unmet. These challenges—complexity, time constraints, and resource scarcity—render traditional rule-based and database-driven verification methods inadequate. The speaker emphasized that siloed, manual processes, such as testbench creation and debugging, consume 40% of the verification workforce’s time, yet fail to deliver the necessary confidence in tape-out readiness.
The industry is undergoing a profound shift, moving from the electrification era, which automated physical labor, to the computation era, and now to the “cognification” era, where cognitive tasks are delegated to AI. By 2030, the semiconductor market is projected to exceed a trillion dollars, with AI as a dominant driver. Generative AI, expected to grow at an 85% compound annual growth rate by 2027, is reshaping infrastructure, services, and software. Meanwhile, the rise of 3D integrated circuits (3D ICs) is set to propel the market from $200 billion to $1 trillion by 2030, introducing complexities in heterogeneous integration, interconnects, power, and thermal management. Data security is another concern, with 8.2 trillion breaches reported in 2023, costing an average of $4.5 million per incident.
Traditional verification, reliant on disconnected simulation, formal, and static methods, struggles to scale. Coverage reports often lack actionable insights, and manual debugging is inefficient. The speaker proposed an AI-driven solution, exemplified by their “Quetsa One” approach, which integrates connected workflows, data-driven insights, and scalable tools. This smarter verification leverages AI in three key areas: specification generation, debugging, and coverage analysis.
In specification generation, AI tools like Property Assist convert plain English or PDF-based design specifications into standardized SystemVerilog assertions, eliminating the need for engineers to master complex languages. These assertions integrate seamlessly with formal verifiers and netlists, while test plans can be generated from the same specifications, ensuring alignment with design intent. This streamlines the process, reducing human effort and maintaining a single source of truth.
For debugging, AI transforms regression testing into “smart regression.” By prioritizing test cases to trigger failures quickly, AI minimizes resource waste. It clusters failures, maps them to specific design changes, and identifies the responsible commits, significantly reducing debugging time. This targeted approach contrasts with traditional methods, where engineers manually sift through extensive logs.
In coverage analysis, analytical AI processes large datasets to identify common expression patterns, creating configurable graphs that highlight critical coverage gaps. This enables engineers to write targeted testbenches, improving coverage quality without relying on arbitrary test additions. By providing actionable insights, AI moves beyond mere numbers to deliver meaningful verification outcomes.
The Costa One approach embodies this shift, offering connected workflows that unify tools across domains, data-driven wisdom to uncover insights, and scalable tools to handle growing verification loads. The speaker urged the verification community to adapt, questioning siloed and static processes to embrace AI’s potential. By fostering adaptability and innovation, AI-driven verification promises to enhance productivity, reduce time-to-market, and ensure robust chip designs in an increasingly complex semiconductor landscape.
Also Read:
Building Trust in AI-Generated Code for Semiconductor Design
Microsoft Discovery Platform: Revolutionizing Chip Design and Scientific Research
Google Cloud: Optimizing EDA for the Semiconductor Future
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