Building Trust in AI-Generated Code for Semiconductor Design

On July 9, 2025, a compelling session at DACtv by Vishal Moondrha of Perfroce addressed a critical challenge in the semiconductor industry: building trust in AI-generated code. The speaker highlighted the unique hurdles of integrating generative AI into semiconductor design, emphasizing issues like data provenance, quality, and intellectual property (IP) management. As AI becomes integral to designing analog circuits, RTL, and other components, these concerns must be tackled to unlock its full potential.

The semiconductor industry faces distinct challenges compared to other sectors. First, there is heightened sensitivity to liability and data provenance. Unlike software development, where errors can often be patched quickly, mistakes in chip design are costly and difficult to rectify, especially as designs progress. A single error in generated code can lead to expensive rework, making reliability paramount. Additionally, data quality is a concern, as every company has unique standards and workflows developed over years. Ensuring that AI-generated code adheres to these standards is critical to maintaining design integrity.

Another significant issue is the legal and ethical use of data for training AI models. Semiconductor designs often incorporate external IP, which may carry royalty obligations or export control restrictions. Using such IP to train AI models without proper authorization risks legal violations and data leakage. For instance, training a model on proprietary IP could inadvertently produce outputs that violate licensing agreements, exposing companies to liability. Furthermore, highly sensitive IPs, such as those with geographical restrictions, must be excluded from training datasets to comply with regulations.

To address these challenges, the speaker proposed a robust IP lifecycle management system. By treating every design block as an IP, whether internally developed, purchased, or reused from prior projects, companies can attach traceability and metadata to each block. This approach ensures clear data provenance, allowing teams to track the origin, ownership, and usage rights of each IP. For example, metadata might include technical specifications, workflow outputs, or verification results, providing context that enhances the AI model’s understanding of the design.

The proposed workflow involves breaking down designs into hierarchical IPs, each with a defined lifecycle. This modular approach enables companies to set rules for which IPs can be used for training. For instance, IPs with export controls or proprietary restrictions can be flagged to prevent their inclusion in datasets. Tools like those from Siemens, in collaboration with Perforce, generate metadata through IP validation and quality assurance processes, which can be linked to specific IP versions. This ensures that AI models are trained on compliant, high-quality data.

The speaker also emphasized the importance of traceable data pipelines. A typical training workflow starts with raw design files and metadata, which are pre-processed, cleaned, and split into training, validation, and testing sets. By maintaining traceability throughout this pipeline, companies can audit the data’s journey, ensuring no unauthorized IPs are included. This is particularly crucial as design data evolves, with incremental updates like bug fixes or new features requiring continuous tracking to maintain accuracy.

Implementing such a system offers multiple benefits. It mitigates data leakage risks, simplifies data management by modularizing IPs, and supports compliance with legal and regulatory requirements. By using data management tools like SQL databases, Perforce, or Git, companies can avoid ad-hoc data handling, ensuring that training datasets are sourced from managed repositories. Additionally, modeling AI models themselves as IPs allows tracking of which LLM version was used, enhancing transparency.

This approach fosters innovation by providing a trusted framework for AI-driven design, enabling semiconductor companies to leverage generative AI confidently while safeguarding IP and ensuring compliance.

Also Read:

Microsoft Discovery Platform: Revolutionizing Chip Design and Scientific Research

Google Cloud: Optimizing EDA for the Semiconductor Future

Synopsys FlexEDA: Revolutionizing Chip Design with Cloud and Pay-Per-Use