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CEO Interview with Darin Davis of SILICET

CEO Interview with Darin Davis of SILICET
by Daniel Nenni on 07-11-2025 at 6:00 am

Key Takeaways

  • SILICET focuses on innovative LDMOS architecture to enhance cost, performance, and reliability for semiconductor IP licensing.
  • The company offers a scalable source-side LDMOS design that minimizes on-resistance and enhances device performance while integrating with existing BCD nodes.
  • SILICET addresses challenges such as parasitic bipolar effects in LDMOS devices, providing solutions that improve Safe Operating Area and reliability.

Davis Silicet silicetSILICET logo

With over 30 years of diverse industry experience, Darin leads SILICET, a semiconductor IP licensing firm.   He spearheaded a strategic pivot to focus on a seamless LDMOS innovation that delivers unmatched cost, performance and reliability advantages – backed by a robust global patent portfolio.  Prior to co-founding SILICET, he held business development roles at Coventor and VLSI Technology.

Tell us about your company?

Silicet develops and licenses IP for semiconductors.  The current focus is delivering a scalable source-side LDMOS architecture that minimizes on-resistance for a given breakdown voltage, while simultaneously enhancing Safe Operating Area, mitigating fast-transient EOS and boosting HCI reliability.

Silicet’s IP transparently integrates with any existing BCD node, providing increased device performance at a lower total production cost.  With a global IP patent portfolio in the United States, Taiwan, China, and Europe, Silicet’s IP has already been integrated in mature BCD technology offerings.

What problems are you solving?

All MOSFETs have an inherent parasitic bipolar, which can cause catastrophic snapback in Lateral DMOS devices, where the traditional mitigation approach complicates source/body engineering.  Silicet’s source-side engineering provides LDMOS designers with several simultaneous advantages:

+   provides the lowest specific on-resistance (RSP)

+   virtually eliminates the parasitic NPN

+   enhances SOA and reliability mechanisms

+   avoids punch through of self-aligned body

+   enables a new Retrograde Body to boost breakdown voltage

+   seamlessly fits into any BCD process

Silicet’s comprehensive solution provides new design trade-offs which are not available from existing device architectures, enabling LDMOS designers to leverage their know-how to optimize LDMOS devices for lowest Rsp at a given BVdss, with increasing benefits as operating voltage decreases from 16V to 5V.

This innovation seamlessly integrates with existing lithography techniques and silicidation process flows, enabling ~25% cost/performance benefits while enhancing reliability –  thereby extending the useful life of existing BCD processes and associated installed process equipment.

What new features/technology are you working on?

Silicet’s innovative IP provides multiple “knobs” where LDMOS designers can leverage their know-how to optimize devices for demanding circuit applications.

There are three key aspects to Silicet’s novel BCD technology innovation.

First, Silicet’s Hybrid Source solution minimizes poly-to-poly pitch on the source side, enabling lowest on-resistance for devices at 5v to 28V operating voltage over their conventional counterparts, while providing performance advantages inaccessible from conventional LDMOS devices, opening new opportunities to minimize gate capacitance, leverage high drive current and faster switching speed to optimize GPU/CPU power conversion devices.

A second element is using the Retrograde Body to manipulate the source e-field, providing a new knob to minimize on-resistance for a given drift length, while simultaneously enhancing HCI reliability; which dramatically improves performance and reliability for 5V to 16Vop devices.

The third element takes advantage of novel mobility/carrier injection to provide unique transconductance and very high-drive current benefits – boosting unity gain ~3X.  This breakthrough device enhancement avoids the process complications (deep S/D, Halo, LDD, etc.) which are required to overcome short channel effects; significantly simplifying the LDMOS architecture for 28/40/55/65nm BCD solutions.

What does the competitive landscape look like and how do you differentiate?

The primary market for power conversion devices includes systems requiring low on-state resistance and efficient power management, such as servers (DC-DC converters & integrated modules), automotive (motor drivers & load switches) and power management ICs (PMICs) for portable consumer electronics and Class-D audio applications.

Foundries and IDMs are using existing approaches to incrementally refine LDMOS device performance.  Our source-only innovation provides a generational leap in benefits, simultaneously delivering superior electrical performance, increased reliability and smaller die size on any BCD node.

Silicet doesn’t create the LDMOS design,

               we dramatically enhance the LDMOS you design!

While our innovation provides more compelling benefits at lower operating voltage and shorter BCD nodes, high voltage (40V to 100V operation) devices can still leverage the enhanced SOA and fast-transient EOS benefits in circuit applications that demand robust and reliable operation – including RF-LDMOS applications.

Silicet’s IP is a gamechanger for LDMOS designers, enabling semiconductor firms to dramatically differentiate performance, cost, and reliability.

  • Performance Edge: Readily differentiates products in competitive markets
    Lowest Rsp, Lowest Gate Capacitance, Highest Drive Current
  • Faster Time-to-Market: Transparently integrates with any BCD node
    Realize “next node” benefits from existing lithography (no capex required),
    while reducing technical risks and lowering adoption barriers.
  • Enhanced Reliability: Ensures robust device operation in challenging applications
    The architecture improves Safe Operating Area (SOA), mitigates fast-transient
    Electrical Overstress (EOS), and boosts Hot Carrier Injection (HCI) reliability.
  • Maximize ROI : Leverage Know-How to target diverse LDMOS applications
    (e.g. – DC-DC, PMICs, motor drivers, and RF devices)
    Achieve higher margins in demanding, cost-sensitive market applications
    Optimize resource utilization (device/process/design expertise)

These factors collectively empower semiconductor companies to rapidly achieve distinct competitive advantages, positioning them to quickly capture new opportunities and improve profitability from a single, source-side innovation.

Final comments?

Not only has X-FAB been an instrumental development partner, but also they leveraged their process/device know-how to commercialize 2nd generation ultra-low Rsp devices in XT018, X-FAB’s leading 180 nm BCD-on-SOI technology platform. This simple solution offers customers Rsp reductions of 50% (5.5V) to 30% (28V), while also enhancing robust operation and reliability in challenging automotive and industrial applications.

X-FAB’s XT018 MV Gen 2

How do customers normally engage with your company?

Silicet is actively engaging strategic partners who either want to uplift an existing BCD process or future-proof an advanced BCD node.  Let’s work together to leverage your LDMOS device/process know-how to enable breakthrough solutions.

Contact SILICET

Join the LDMOS evolution!

Also Read:

CEO Interview with Peter L. Levin of Amida

CEO Interview with John Akkara of Uptime Crew

CEO Interview with Dr. Naveen Verma of EnCharge AI

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