CEO Interview with Richard Hegberg of Caspia Technologies

Rick has a long and diverse career in the semiconductor industry. He began as VP of sales at Lucent Microelectronics. He has held executive roles at several high-profile companies and participated in several acquisitions along the way. These include NetApp, SanDisk/WD, Atheros/Qualcomm, Numonyx/Micron, ATI/AMD, and VLSI Technology.

Rick was CEO of three semiconductor start-ups. He has a deep knowledge and passion for semiconductor systems with a special focus on analog and AI. Rick joined Caspia Technologies as CEO in September 2024.

Tell us about your company

Caspia Technologies was born out of pioneering work in cybersecurity at the University of Florida in Gainesville.  The founding team includes Dr. Mark Tehranipoor, Department Chair of Electrical and Computer Engineering. Mark is also the founding director of the Florida Institute for Cybersecurity Research.

He and his research team have driven an expanded understanding of the complex world of cybersecurity. This team began developing unique GenAI assisted tools to assure new chip designs are resistant to current and future cyberattacks. That commercial application of the team’s work is what created Caspia Technologies and got my attention to lead the effort.

What problems are you solving?

Caspia is delivering technology and know-how to ensure chip designs are resistant to cyberattacks. If you think about current production chip design flows, there are well-developed processes to verify the functionality, timing and power of new chip designs. What is missing is a process to verify how secure and resistant to attack these chips designs are. A security verification flow is needed, and Caspia is delivering that.

There is more to this story. We all know that AI is driving many new and highly complex chip designs. Design teams are now using AI technology to make it easier and faster to design the required chips. Using AI to design AI chips if you will. While this approach has shown substantial results, there are two critical risks that emerge.

First, the vast data sets that are being used to train AI models are typically not managed and secured appropriately. This opens the door to faulty design practices. And second, these same AI algorithms can be used to mount very sophisticated cyberattacks. AI makes it easier to design chips but also easier to attack those same chips.

Using GenAI technology and a deep understanding or cyberattack methods, Caspia is addressing these problems.

What application areas are your strongest?

Assurance of security at the hardware level is our focus and our core strength. We are presently deploying a GenAI assisted security platform that examines pre-silicon designs using three approaches.

First, we perform static checking of RTL code to identify design practices that can lead to security weaknesses. The tool also helps designers fix the problems it finds. We us a large set of checks that is constantly updated with our security trained large language models (LLMs).

Second, we use GenAI to create security-based assertions that can be fed to standard formal verification tools. This opens the door to deep analysis of new designs from a security standpoint.

And third, we use GenAI to set up scenarios using standard co-simulation and emulation technology to ensure the design is indeed resistant to real-world cyberattacks.

What keeps your customers up at night?

That depends on the customer. Those that are new to the use of AI technology for chip design may not realize the risks they are facing. Here, we provide training to create a deeper understanding of the risks and how to address them.

Design teams that are already using AI in the design flow better understand the risks they face. What concerns these teams usually falls into two categories:

1. How can I protect the data I am using to train my LLMs, and how can I use those LLMs more effectively?
2. How can I be sure my design is resistant to current and future cyberattacks?

Caspia’s security platform addresses both of these issues.

What does the competitive landscape look like and how do you differentiate?

There are many commercially available IP blocks that claim various degrees of security hardness. There are also processes, procedures and tools that can help ensure a better design process.

But there is no fully integrated platform that uses GenAI to verify new chip designs are as secure as they can be. This is the unique technology that is only available from Caspia.

What new features/technology are you working on?

Our current security verification platform is a great start. This technology has received an enthusiastic response from both small and very large companies. The ability to add a security verification to your existing design flow is quite compelling. No new design flow, just new security insights.

We are constantly updating our GenAI models to ensure we are tracking and responding to the latest threats. Beyond that, we will be adding additional ways to check a design. Side-channel assessment, fault injection, IP protection and silicon backside protection are all on our roadmap.

How do customers normally engage with your company?

We are starting to be visible at more industry events. For example, we are a Corporate Sponsor at the IEEE International Symposium on Hardware Oriented Security and Trust (HOST) in San Jose on May 5-8 this year and Dr. Tehranipoor will be giving a SkyTalk at DAC as well in June. You can stop by and see us at these events. You can also reach out to us via our website here. We’ll take it from there.

Also Read:

CEO Interview with Dr. Michael Förtsch of Q.ANT

Executive Interview with Leo Linehan, President, Electronic Materials, Materion Corporation

CEO Interview with Ronald Glibbery of Peraso

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