Dr. Thang Tran is an innovator in modern computing, drawing inspiration from pioneers like Seymour Cray, Thornton, and Tomasulo. His work leverages the simplicity of the RISC-V ISA to advance microprocessor efficiency, integrating vector processing and scoreboarding principles foundational to early supercomputing. Thang has adapted Tomasulo’s dependency checking algorithm to enable ahead-of-time instruction scheduling, improving CPU execution throughput. His contributions extend to AI and ML applications, ensuring processors are optimized for high-speed, parallel computation in today’s most demanding workloads.
Tell us about your company.
Simplex Micro was incorporated in December 2021 with a focus on developing processors for AI and ML applications. Our foundation is built on RISC-V, an open-source ISA that differs significantly from x86 and ARM. Unlike traditional architectures, RISC-V fosters innovation in microprocessor design while offering significant advantages in performance, power efficiency, and area optimization (PPA).
What problems are you solving?
The rapid expansion of AI, natural language processing (NLP), and augmented/virtual reality (AR/VR) demands more efficient computing solutions. RISC-V’s vector ISA offers key advantages over both GPUs and SIMD-based architectures such as Intel AVX and ARM Neon. A new class of design—incorporating ahead scheduling with deterministic out-of-order execution—opens up new possibilities for AI and data center applications, improving efficiency and scalability.
What application areas are your strongest?
Our configurable and programmable vector processor is well-suited for a wide range of applications, from AI edge computing to large-scale data centers. Meta’s MTIA project has already demonstrated the potential of vector processors in data centers, and our approach builds on this foundation to deliver even greater efficiency and performance.
What keeps your customers up at night?
While many companies emphasize performance, power consumption remains a primary concern for our customers. Our simplified design delivers out-of-order execution without requiring register renaming, minimizing area while maintaining high efficiency. Additionally, our deterministic approach to time-based scheduling significantly reduces power consumption. Another critical challenge is memory latency. Our vector processor architecture is designed to tolerate load latency when fetching from memory—whether it takes 10 cycles or 100 cycles, performance remains unaffected. Unlike conventional designs, our execution model is independent of load latency, ensuring consistent performance. Furthermore, we leverage RISC-V’s customization capabilities, enabling customers to integrate their own proprietary custom instructions to enhance both performance and security.
What does the competitive landscape look like, and how do you differentiate?
We have developed the first-ever processor designed with a time-based execution model. In the IP market, we currently outperform competitors by at least 2X in performance. Looking ahead, we plan to expand into the chiplet market, bringing the same disruptive impact to a broader range of applications.
What new features or technologies are you working on?
We started with an innovative vector processor design and have an ambitious roadmap ahead. Our future developments include adding multithreading, automotive optimizations, and matrix accelerators while continuously adapting to industry demands. Unlike traditional fixed-configuration processors, our designs are fully parameterized, allowing for maximum flexibility, configurability, and customization to meet diverse application requirements.
How do customers normally engage with your company?
As a stealth-mode startup, we engage selectively with early adopters, industry partners, and strategic collaborators under NDA. Customers typically connect through direct introductions, technical briefings, and proof-of-concept discussions. We focus on co-developing solutions for AI, cloud, and HPC, with plans to expand through early access programs and pilot deployments.
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