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Two More Transistor-Level Companies at DAC

Two More Transistor-Level Companies at DAC
by Daniel Payne on 07-02-2011 at 8:38 pm

In my rush on Wednesday at DAC I had almost over-looked the last two companies I talked with: Invarian and AnaGlobe. These last two I had hand-written notes on paper, so I just got to the bottom of my inbox tonight to write up the final trip reports.

Invarian
Jens Andersen and Vladimir Schellbach gave me an overview of tools that perform… Read More


Cadence to launch PCIe gen-3 (8 GT/s) IP and VIP: fruit of Denali acquisition

Cadence to launch PCIe gen-3 (8 GT/s) IP and VIP: fruit of Denali acquisition
by Eric Esteve on 06-28-2011 at 10:59 am

The recent announcement from Cadence, officially launching the PCI Express 3.0 Controller IP, as well as the associated Verification IP (VIP), made of Compliance Management System (CMS) which provides interactive, graphical analysis of coverage results, and PureSuite which provides the PCIe associated test cases, clearlyRead More


HDMI vs DisplayPort?… DiiVA is the answer from China!

HDMI vs DisplayPort?… DiiVA is the answer from China!
by Eric Esteve on 06-26-2011 at 9:40 am

During the early 2000’s, when OEM starting to question the use of LVDS to interface with display devices, two standards has emerged: High-Definition Multimedia Interface (HDMI) and DisplayPort. HDMI has been developed by silicon Image, surfing on the success of Digital Video Interface (DVI), and was strongly supportedRead More


Semiconductor IP State of the Union

Semiconductor IP State of the Union
by Daniel Nenni on 06-19-2011 at 10:15 am

After the mega IP acquisitions last year by Cadence (Denali) and Synopsys (Virage) a lot of people are wondering what is next for the commercial Semiconductor IP market. Let me offer my opinion as a person who works closely with foundries and their top customers and the opinion of Dr. Eric Esteve, an expert on interface IP.

The commercial… Read More


DRC tool guns for Calibre at DAC

DRC tool guns for Calibre at DAC
by Daniel Payne on 06-17-2011 at 6:48 pm

Intro
Across the aisle from the Mentor booth at DAC sat a DRC tool competitor to Calibre. I received an update from Randy Smith of Polyteda on Wednesday afternoon, my last EDA vendor of the week.

Ravi Ravikumar, Randy Smith

Notes
Randy Smith – CEO (February 2011) [former founder is gone]- 1979 at HP developing internal tools
–… Read More


Circuit Simulation update from Cadence at DAC

Circuit Simulation update from Cadence at DAC
by Daniel Payne on 06-17-2011 at 6:06 pm

Intro
In the bloggers suite I met with John Pierce of Cadence last Wednesday to get an update on what’s new with circuit simulation at DAC this year.

Notes

News – market is growing, RF CMOS simulation is growing
– Show on RF (MTT – Microwave Technology ) this week, sharing a booth with AWR this week
Recent news withRead More


Reduced IC leakage at DAC

Reduced IC leakage at DAC
by Daniel Payne on 06-17-2011 at 5:46 pm

Intro
Neal Carney, VP of Marketing at Tela Innovations provided me an update at DAC last week. Their company partnered with TSMC to reduce leakage in IC designs by biasing the gate lengths on your paths that are non-critical to timing.

Notes

Why do this?
– Reduce leakage
– Increase gate lengths on paths with slack
–… Read More


Cadence spinout at DAC

Cadence spinout at DAC
by Daniel Payne on 06-17-2011 at 5:37 pm

Intro
I remember when Celestry was acquired by Cadence because that gave them a hierarchical Fast SPICE simulator to compete with HSIM. In 2007 part of Celestry spun out from Cadence and became Proplus, which now offers a SPICE simulator called NanoDesigner.

Notes
Proplus – US company, founded in 1995 (Used to be Celestry, acquired… Read More


RLCK reduction tool at DAC

RLCK reduction tool at DAC
by Daniel Payne on 06-17-2011 at 5:23 pm

Intro
Most EDA parasitic extraction tools have built-in RC reduction with no user control however at DAC I learned how Edxact offers a stand-along RLCK reduction tool for IC designers that want more control over what happens to their extracted netlists.


Daniel Borgraeve (on right)

Notes
Edxact
– Started seven years ago… Read More


Ciranova Update at DAC

Ciranova Update at DAC
by Daniel Payne on 06-17-2011 at 4:55 pm

Intro
Ciranova offers you an alternative for analog layout automation besides Cadence Virtuoso. Mark Nadim provided me an update at DAC last Wednesday.

Notes
New in 2011
– New GUI with schematic, layout and constraints
o Cross probing between all three windows
– Schematic for constraint entry
o Can start with a blank… Read More