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Podcast EP355: An Overview of the Q126 Electronic Design Market Data Report with Wally Rhines

Podcast EP355: An Overview of the Q126 Electronic Design Market Data Report with Wally Rhines
by Daniel Nenni on 07-13-2026 at 8:00 am
Categories: ESD Alliance, Semiconductor Services

Daniel is joined by Wally Rhines, CEO of Silvaco to discuss the Electronic Design Market Data report that was just released. Wally is the industry coordinator for the EDA data collection program called EDMD. SEMI and the Electronic System Design Alliance collect data from almost all of the electronic design automation companies… Read More

July 12, 2026July 13, 2026

AI Driven Semiconductor Systems

AI Driven Semiconductor Systems
by Daniel Nenni on 07-12-2026 at 8:00 pm
Categories: NetApp, Semiconductor Services

AI-driven semiconductor systems are the next major transformation in chip design and manufacturing. The central idea is that semiconductor workflows are becoming too complex, too data-intensive, and too time-sensitive to be managed only through traditional human-driven engineering processes. Modern chips now involve… Read More

July 9, 2026August 6, 2026

Consolidation and Competition: Who is Winning the $4.5 Billion Interface IP Race?

Consolidation and Competition: Who is Winning the $4.5 Billion Interface IP Race?
by Kalar Rajendiran on 07-09-2026 at 2:00 pm
Categories: AI, Chiplet, IP, IPnest, Semiconductor Services
1 Comment

The semiconductor landscape is currently undergoing a structural transformation as the “Data-Centric Shift” moves the industry’s center of gravity from smartphones toward High-Performance Computing (HPC) and AI infrastructure.

This transition is clearly validated by TSMC’s 2025 filings, which show… Read More

July 9, 2026July 9, 2026

SemiAnalysis EDA Market Primer – Market Dynamics, Cadence, Synopsys, Siemens, China EDA Rise

SemiAnalysis EDA Market Primer – Market Dynamics, Cadence, Synopsys, Siemens, China EDA Rise
by Daniel Nenni on 07-09-2026 at 10:00 am
Categories: EDA, Semiconductor Services

Electronic Design Automation, or EDA, is the software infrastructure that transforms a hardware specification into a manufacturable integrated circuit. At advanced process nodes, the problem is no longer simply drawing transistors or connecting gates. A modern system-on-chip contains billions of standard cells, hundreds… Read More

June 25, 2026July 9, 2026

WEBINAR: Why Google Cloud NetApp Volumes Matter for Modern EDA Workloads

WEBINAR: Why Google Cloud NetApp Volumes Matter for Modern EDA Workloads
by Daniel Nenni on 06-25-2026 at 2:00 pm
Categories: Events, NetApp, Semiconductor Services

In this webinar, Google Cloud and NetApp explore how semiconductor companies can address the growing infrastructure demands of modern Electronic Design Automation (EDA) workflows. As process technologies continue to advance and chip designs become increasingly complex, engineering teams require scalable, high-performance… Read More

June 23, 2026June 22, 2026

How Samtec Blazes a Trail to 224/448 Gbps at DesignCon 26

How Samtec Blazes a Trail to 224/448 Gbps at DesignCon 26
by Mike Gianfagna on 06-23-2026 at 6:00 am
Categories: AI, Events, Samtec, Semiconductor Services

I recently covered what Samtec was doing at DesignCon 26. Samtec has a tendency to dominate any show it attends in multiple dimensions. The prior post focused on the company’s contributions to the technical agenda and the high-profile experts in attendance. While all that is interesting and valuable, attending a large show like… Read More

June 22, 2026June 22, 2026

AION Silicon: Architecting Smarter SoCs with RISC-V: Balancing Performance, Flexibility, and Risk

AION Silicon: Architecting Smarter SoCs with RISC-V: Balancing Performance, Flexibility, and Risk
by Daniel Nenni on 06-22-2026 at 10:00 am
Categories: Aion Silicon, IP, RISC-V, Semiconductor Services

As semiconductor complexity accelerates across AI, automotive, and edge computing markets, SoC architecture has become a critical determinant of commercial success. Modern silicon programs must simultaneously achieve aggressive performance-per-watt targets, support evolving workloads, and maintain manageable development… Read More

June 15, 2026June 16, 2026

Agentic AI and the Future of Chip Design: From Productivity Tool to Engineering Partner

Agentic AI and the Future of Chip Design: From Productivity Tool to Engineering Partner
by Kalar Rajendiran on 06-15-2026 at 6:00 am
Categories: AI, Breker Verification Systems, ChipAgents AI, EDA, ESD Alliance, Moores Lab (AI), Semiconductor Services, Silvaco, Verific

ESDA Panel Session June 10, 2026 IMG 6708

Highlights from a recent panel session moderated by Ed Sperling (Semiconductor Engineering) featuring Walden Rhines (Silvaco), Vincent Wong (Verific), Dave Kelf (Breker Verification Systems), Shelly Henry (MooresLab AI), Ann Wu (Silimate), and Cindy Cui (ChipAgents). The panel session was hosted by Electronic System … Read More

June 7, 2026June 8, 2026

CEO Interview with Chuck Gershman of Owl Autonomous Imaging

CEO Interview with Chuck Gershman of Owl Autonomous Imaging
by Daniel Nenni on 06-07-2026 at 4:00 pm
Categories: CEO Interviews, Semiconductor Services, Silicon Catalyst

Chuck Gershman is the CEO and co-founder of Owl Autonomous Imaging. He has spent more than 30 years in semiconductors, AI imaging, computer vision, and autonomous sensing technologies across executive management, engineering, marketing, business development, and operations.

Chuck is a Drexel University College of Engineering… Read More

June 4, 2026July 24, 2026

Alchip Accelerates on AI ASIC Demand

Alchip Accelerates on AI ASIC Demand
by Daniel Nenni on 06-04-2026 at 8:00 am
Categories: Alchip, Semiconductor Services

Alchip Technologies reported improved financial results for the first quarter, reflecting continued momentum in advanced artificial intelligence (AI), high-performance computing (HPC), and custom ASIC demand. The company cited stronger customer engagement in leading-edge semiconductor designs and accelerating tape-out… Read More

Verification IP proves essential for PCIe GEN5
Assertion

— Akshay Sarup on August 18, 2026
ASML’s Path to Lithography Dominance—and the Coming Maskless Revolution
Yup.... it is coming ....

— Rahul Razdan on August 16, 2026
ASML’s Path to Lithography Dominance—and the Coming Maskless Revolution
ASML bought a company that worked on massive parallel ebeam lithography in 2019. That company, Mapper, went bankrupt and ASML…

— jnieland on August 14, 2026
ASML’s Path to Lithography Dominance—and the Coming Maskless Revolution
The stochasticity of e-beam writing has been mentioned by the tool makers some years ago. There's already multi-beam for mask…

— Fred Chen on August 14, 2026
Claude as an EDA Tool Wiki
It is really being done at the very front end of chip design. Just the tip of the iceberg of…

— Daniel Nenni on August 13, 2026
The Silicon Shield Has Never Been Stronger!
Agreed. Great movies! War Games was when I just finished my undergrad and used my graduation gifts to buy an…

— Daniel Nenni on August 12, 2026
Claude as an EDA Tool Wiki
Is this something that is really being done inside semiconductor houses, or is this a proposal?

— Debamitro Chakraborti on August 11, 2026
Synopsys and Intel Foundry Enable System-Level Design on Intel 14A
Hopefully the yield will be as expected

— chiro.lentz on August 10, 2026

Hot Chips 2026

Small Satellite Conference

SPIE Optics + Photonics 2026

CadenceLIVE China

Webinar: Advanced Packaging at Scale: Power, Performance, and Reliability in the Chiplet Era

Podcast EP355: An Overview of the Q126 Electronic Design Market Data Report with Wally Rhines

AI Driven Semiconductor Systems

Consolidation and Competition: Who is Winning the $4.5 Billion Interface IP Race?

SemiAnalysis EDA Market Primer – Market Dynamics, Cadence, Synopsys, Siemens, China EDA Rise

WEBINAR: Why Google Cloud NetApp Volumes Matter for Modern EDA Workloads

How Samtec Blazes a Trail to 224/448 Gbps at DesignCon 26

AION Silicon: Architecting Smarter SoCs with RISC-V: Balancing Performance, Flexibility, and Risk

Agentic AI and the Future of Chip Design: From Productivity Tool to Engineering Partner

CEO Interview with Chuck Gershman of Owl Autonomous Imaging

Alchip Accelerates on AI ASIC Demand

Recent Forum Threads

Ian's take on the new Cerebras Wafer Scale Engine 3-Turbo and CS-4 rack.

Socionext plans to tape out a compute chiplet on TSMC A14 in 2026-Sep

Intel CEO Hints Chipzilla’s Return To Making Memory, As He Teases “New Memory Architecture” & 3D Stacking To Tackle The DRAM Wall

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Silicon Surge: Samsung Cashes In on the AI Chip Crunch

AI has made the lives of chip designers harder, not easier

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Intel Corporation to Participate in Upcoming Investor Conference

Alibaba’s TSMC 5nm RISC-V CPU Opens a New Vertical-Integration

Samsung’s 3D-Memory Roadmap Reshapes AI Computing

Recent Article Comments

Verification IP proves essential for PCIe GEN5

ASML’s Path to Lithography Dominance—and the Coming Maskless Revolution

ASML’s Path to Lithography Dominance—and the Coming Maskless Revolution

ASML’s Path to Lithography Dominance—and the Coming Maskless Revolution

Claude as an EDA Tool Wiki

The Silicon Shield Has Never Been Stronger!

Claude as an EDA Tool Wiki

Synopsys and Intel Foundry Enable System-Level Design on Intel 14A