SILVACO 073125 Webinar 800x100
WP_Term Object
(
    [term_id] => 178
    [name] => IP
    [slug] => ip
    [term_group] => 0
    [term_taxonomy_id] => 178
    [taxonomy] => category
    [description] => Semiconductor Intellectual Property
    [parent] => 0
    [count] => 1862
    [filter] => raw
    [cat_ID] => 178
    [category_count] => 1862
    [category_description] => Semiconductor Intellectual Property
    [cat_name] => IP
    [category_nicename] => ip
    [category_parent] => 0
    [is_post] => 
)

AI System Connectivity for UCIe and Chiplet Interfaces Demand Escalating Bandwidth Needs

AI System Connectivity for UCIe and Chiplet Interfaces Demand Escalating Bandwidth Needs
by Kalar Rajendiran on 05-27-2024 at 10:00 am

Alphwave Semi UCIe PHY Support for All Package Types

Artificial Intelligence (AI) continues to revolutionize industries, from healthcare and finance to automotive and manufacturing. AI applications, such as machine learning, deep learning, and neural networks, rely on vast amounts of data for training, inference, and decision-making processes. As AI algorithms become … Read More


Webinar – CHERI: Fine-Grained Memory Protection to Prevent Cyber Attacks

Webinar – CHERI: Fine-Grained Memory Protection to Prevent Cyber Attacks
by Mike Gianfagna on 05-27-2024 at 6:00 am

Webinar – CHERI Fine Grained Memory Protection to Prevent Cyber Attacks

Cyber attacks are top of mind for just about everyone these days. As massive AI data sets become more prevalent (and more valuable), data security is no longer “nice to have”. Rather, it becomes critical for continued online operation and success. The AI discussion is a double-edged sword as well. While AI enables many new and life-changing… Read More


CEO Interview: Barry Paterson of Agile Analog

CEO Interview: Barry Paterson of Agile Analog
by Daniel Nenni on 05-24-2024 at 6:00 am

Agile Analog CEO Barry Patterson

Agile Analog is transforming the world of analog IP with Composa™, its innovative, highly configurable, multi-process analog IP technology.  Agile Analog has developed a unique way to automatically generate analog IP that meet the customer’s exact specifications, for any foundry and on any process, from legacy nodes right … Read More


An open letter regarding Cyber Resilience of the UK’s Critical National Infrastructure

An open letter regarding Cyber Resilience of the UK’s Critical National Infrastructure
by admin on 05-20-2024 at 10:00 am

Codasip UK Security Letter 1

Codasip announced a commercially available RISC-V processor with CHERI for license in October of 2023 and is demonstrating technology for IP provenance. 

Dear Members of the Science, Innovation and Technology Committee,

Let me start by applauding your hearing on 24 April 2024, and in particular the evidence of Professor John… Read More


CEO Interview: Roger Espasa of Semidynamics

CEO Interview: Roger Espasa of Semidynamics
by Daniel Nenni on 05-17-2024 at 6:00 am

Roger Espasa

Roger Espasa is the CEO and founder of Semidynamics, an IP supplier of two RISC-V cores, Avispado (in-order) and Atrevido (out-of-order) supporting the RISC-V vector extension and Gazzillion(tm) misses, both targeted at HPC and Artificial Intelligence. Prior to the foundation of the company, Roger was Technical Director/Distinguished… Read More


A Recipe for Performance Optimization in Arm-Based Systems

A Recipe for Performance Optimization in Arm-Based Systems
by Bernard Murphy on 05-16-2024 at 6:00 am

Performance cookbook for Arm min (1)

Around the mid-2000’s the performance component of Moore’s Law started to tail off. That slack was nicely picked up by architecture improvements which continue to march forward but add a new layer of complexity in performance optimization and verification. Nick Heaton (Distinguished Engineer and Verification Architect at… Read More


ARC-V portfolio plus mature software IP targets three tiers

ARC-V portfolio plus mature software IP targets three tiers
by Don Dingee on 05-13-2024 at 10:00 am

ARC-V portfolio from Synopsys

Synopsys is bridging its long-running ARC® processor IP strategy into a RISC-V architecture – Bernard Murphy introduced the news here on SemiWiki last November. We’re getting new insight from Synopsys on its ARC-V portfolio and how they see RISC-V IP plus their mature software development toolchain IP fitting customer needs… Read More


Webinar: Fine-grained Memory Protection to Prevent RISC-V Cyber Attacks

Webinar: Fine-grained Memory Protection to Prevent RISC-V Cyber Attacks
by Daniel Nenni on 05-10-2024 at 8:00 am

EW Award 24 Logo winner safety Security coloured RGB 300dpi 960x117

Most organizations are aware of cybercrime attempts such as phishing, installing malware from dodgy websites or ransomware attacks and undertake countermeasures. However, relatively little attention has been given to memory safety vulnerabilities such as buffer overflows or over-reads. For decades, the industry has created… Read More


An Enduring Growth Challenge for Formal Verification

An Enduring Growth Challenge for Formal Verification
by Bernard Murphy on 05-08-2024 at 6:00 am

Math blackboard min

A high-quality verification campaign including methods able to absolutely prove the correctness of critical design behaviors as a complement to mainstream dynamic verification? At first glance this should be a no-brainer. Formal verification offers that option and formal adoption has been growing steadily, now used in around… Read More


The latest ideas on time-sensitive networking for aerospace

The latest ideas on time-sensitive networking for aerospace
by Don Dingee on 05-06-2024 at 10:00 am

Aircraft domain requirements for time sensitive networking in aerospace

Time-sensitive networking for aerospace and defense applications is receiving new attention as a new crop of standards and profiles approaches formal release, anticipated before the end of 2024. CAST, partnering with Fraunhofer IPMS, has developed a suite of configurable IP for time-sensitive networking (TSN) applications,… Read More