Artificial Intelligence (AI) continues to revolutionize industries, from healthcare and finance to automotive and manufacturing. AI applications, such as machine learning, deep learning, and neural networks, rely on vast amounts of data for training, inference, and decision-making processes. As AI algorithms become … Read More
Semiconductor Intellectual Property
Webinar – CHERI: Fine-Grained Memory Protection to Prevent Cyber Attacks
Cyber attacks are top of mind for just about everyone these days. As massive AI data sets become more prevalent (and more valuable), data security is no longer “nice to have”. Rather, it becomes critical for continued online operation and success. The AI discussion is a double-edged sword as well. While AI enables many new and life-changing… Read More
CEO Interview: Barry Paterson of Agile Analog
Agile Analog is transforming the world of analog IP with Composa™, its innovative, highly configurable, multi-process analog IP technology. Agile Analog has developed a unique way to automatically generate analog IP that meet the customer’s exact specifications, for any foundry and on any process, from legacy nodes right … Read More
An open letter regarding Cyber Resilience of the UK’s Critical National Infrastructure
Codasip announced a commercially available RISC-V processor with CHERI for license in October of 2023 and is demonstrating technology for IP provenance.
Dear Members of the Science, Innovation and Technology Committee,
Let me start by applauding your hearing on 24 April 2024, and in particular the evidence of Professor John… Read More
CEO Interview: Roger Espasa of Semidynamics
Roger Espasa is the CEO and founder of Semidynamics, an IP supplier of two RISC-V cores, Avispado (in-order) and Atrevido (out-of-order) supporting the RISC-V vector extension and Gazzillion(tm) misses, both targeted at HPC and Artificial Intelligence. Prior to the foundation of the company, Roger was Technical Director/Distinguished… Read More
A Recipe for Performance Optimization in Arm-Based Systems
Around the mid-2000’s the performance component of Moore’s Law started to tail off. That slack was nicely picked up by architecture improvements which continue to march forward but add a new layer of complexity in performance optimization and verification. Nick Heaton (Distinguished Engineer and Verification Architect at… Read More
ARC-V portfolio plus mature software IP targets three tiers
Synopsys is bridging its long-running ARC® processor IP strategy into a RISC-V architecture – Bernard Murphy introduced the news here on SemiWiki last November. We’re getting new insight from Synopsys on its ARC-V™ portfolio and how they see RISC-V IP plus their mature software development toolchain IP fitting customer needs… Read More
Webinar: Fine-grained Memory Protection to Prevent RISC-V Cyber Attacks
Most organizations are aware of cybercrime attempts such as phishing, installing malware from dodgy websites or ransomware attacks and undertake countermeasures. However, relatively little attention has been given to memory safety vulnerabilities such as buffer overflows or over-reads. For decades, the industry has created… Read More
An Enduring Growth Challenge for Formal Verification
A high-quality verification campaign including methods able to absolutely prove the correctness of critical design behaviors as a complement to mainstream dynamic verification? At first glance this should be a no-brainer. Formal verification offers that option and formal adoption has been growing steadily, now used in around… Read More
The latest ideas on time-sensitive networking for aerospace
Time-sensitive networking for aerospace and defense applications is receiving new attention as a new crop of standards and profiles approaches formal release, anticipated before the end of 2024. CAST, partnering with Fraunhofer IPMS, has developed a suite of configurable IP for time-sensitive networking (TSN) applications,… Read More
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