Banner Electrical Verification The invisible bottleneck in IC design updated 1
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EDA

Electronic Design Automation

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Cadence Expands Integrated Photonics Beachhead

Cadence Expands Integrated Photonics Beachhead
by Mitch Heins on 03-30-2017 at 4:00 pm
Categories: Cadence, EDA, Silicon Photonics

In November of 2016, I made a bold statement that October 20, 2016 would stand as a watershed day in integrated photonics. The reason for this claim was that GLOBALFOUNDRIES proclaimed that integrated photonics was real and here to stay. The same week I wrote an article about Cadence Design Systems securing a photonic beachhead … Read More

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Analyzing All of those IC Parasitic Extraction Results

Analyzing All of those IC Parasitic Extraction Results
by Daniel Payne on 03-30-2017 at 12:00 pm
Categories: EDA, Events

Back at DAC in 2011 I first started to hear about this EDA company named edXact that specialized in reducing and analyzing IC parasitic extraction results. So Silvaco acquired edXact and I wanted to get an update on what is new with their EDA tools that help help you to analyze and manage the massive amount of extracted RLC and even K … Read More

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SNUG 2017 Keynote: Aart de Geus on EDA Fusion!

SNUG 2017 Keynote: Aart de Geus on EDA Fusion!
by Daniel Nenni on 03-30-2017 at 7:00 am
Categories: EDA, Events, Synopsys

I spoke with Aart before his SNUG keynote and found him to be very relaxed and upbeat about EDA and our future prospects which reminded me of my first ever (cringe-worthy) blog, “EDA is Dead”. Now, eight years later, we have what Aart calls “EDA Fusion” to thank for the reemergence of EDA as a semiconductor superpower, absolutely.… Read More

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A Formal Feast

A Formal Feast
by Bernard Murphy on 03-29-2017 at 7:00 am
Categories: EDA, Synopsys

It’s not easy having to deliver one of the last tutorials on the last day of a conference. Synopsys drew that short straw for their tutorial on formal methodologies at DVCon this year. Despite that they delivered an impressive performance, keeping the attention of 60 attendees who said afterwards it was excellent on technical content,… Read More

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Seven Reasons to Use FPGA Prototyping for ASIC Designs

Seven Reasons to Use FPGA Prototyping for ASIC Designs
by Daniel Payne on 03-28-2017 at 12:00 pm
Categories: EDA, FPGA, Open-Silicon

Using an FPGA to prototype your next hardware design is a familiar concept, extending all the way back to the time that the first FPGAs were being produced by Xilinx and Altera. There are multiple competitors in the marketplace for FPGA prototyping, so I wanted to discern more about what the German-based company PRO DESIGN had to … Read More

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Virtual Modeling Drives Auto Systems TTM

Virtual Modeling Drives Auto Systems TTM
by Bernard Murphy on 03-27-2017 at 7:00 am
Categories: Automotive, EDA, Synopsys

The electronics market for automotive applications is distinguished by multiple factors. This is a very fast growing market – electronics now account for 40% of a car’s cost, up from 20% just 10 years ago. New technologies are gaining acceptance, for greener and safer operation and for a more satisfying consumer experience. Platforms… Read More

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How to Design a Custom SoC with Analog, webinar from ARM and Tanner EDA

How to Design a Custom SoC with Analog, webinar from ARM and Tanner EDA
by Daniel Payne on 03-23-2017 at 12:00 pm
Categories: Arm, EDA, Siemens EDA, Tanner EDA

Leading edge SoC designs can contain billions of transistors, cost over $10M to design, and take over 18 months to deliver, but not all SoCs require that much complexity, cost and time. In fact, there is a growing class of SoC designs that integrate the popular ARM Cortex-M0 processor along with analog blocks that work with sensors… Read More

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Samsung Should Just Buy eSilicon Already!

Samsung Should Just Buy eSilicon Already!
by Daniel Nenni on 03-22-2017 at 12:00 pm
Categories: EDA, eSilicon, FinFET, IP, Samsung Foundry, Semiconductor Services

As you all know I’m a big fan of the ASIC business dating back to the start of the fabless semiconductor transformation where anybody could send a design spec to an ASIC company and get a chip back. The ASIC business model also started the smart phone revolution when Samsung built the first Apple SoCs for the iPhones and iPads.

Today … Read More

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SRAM Optimization Saves Power on SOC’s and in Systems

SRAM Optimization Saves Power on SOC’s and in Systems
by Tom Simon on 03-21-2017 at 12:00 pm
Categories: EDA, Magwel

Mobile device designers face the dilemma of reducing power and at the same time maintaining or increasing performance. Consumers will not tolerate increased battery life at the expense of performance. If it were otherwise, designers could simply dial back clock rates. Without this simple cure, the best way to reduce power for… Read More

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Joe Costello and Other Luminaries Keynote at DAC

Joe Costello and Other Luminaries Keynote at DAC
by Daniel Payne on 03-20-2017 at 12:00 pm
Categories: EDA, Events, IoT

The most charismatic EDA CEO that I have ever witnessed is Joe Costello, who formed Cadence by merging SDA (Solomon Design Automation) and ECAD (known for DRC with Dracula). You will be impressed with his Monday keynote at DACon June 19th, starting at 9:15AM. Joe has long since left the EDA world and is currently the CEO of a company… Read More